It's non-inclusive On 1/23/12, Mahmood Naderan <mahmood...@gmail.com> wrote: > seems that asked the question in a hard way. > > In another word, for the classic memory model,I want to know: > 1- if the cache is exclusive or inclusive? > 2- If yes, how can I modify that in config files? > > a simple grep finds both "exclusive" and "inclusive". But I don't know > how to configure that > > Thanks > > On 1/18/12, Mahmood Naderan <mahmood...@gmail.com> wrote: >> Hi >> How does memory respond to L1 misses in classis memory model? When an >> L1 miss occurs, this is propagated to L2. Assume L2 also faces a miss >> so it will propagate to memory controller. >> >> Now when memory is responding, will it hand the block (data or >> instruction) to L2 or it will directly respond to L1? >> -- >> // Naderan *Mahmood; >> > > > -- > -- > // Naderan *Mahmood; > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
-- *thanks®ards * *BISWABANDAN* _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
