Hi How does memory respond to L1 misses in classis memory model? When an L1 miss occurs, this is propagated to L2. Assume L2 also faces a miss so it will propagate to memory controller.
Now when memory is responding, will it hand the block (data or instruction) to L2 or it will directly respond to L1? -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
