ok, I found somethings but nt sure about that. What I understand is: This function in o3/cpu.cc says that fetch stage in o3cpu is connected to icache which came from previous cpu (atomic). Also iew component in o3cpu is connected to dcache which came from previous cpu (atomic).
BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); In another word, when switching cpu from atomic to o3, icache is connected to fetch and dcache is connected to iew. Now the question is, what can I do if I want to do more wiring. For example, I want to connect fetch stage to dcache. What I did was to add another argument: BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort(), fetch.getDcachePort()); and modify the functions definition. However by doing that, the wire from iew to dcache is overwritten by the wire from fetch to dcache. Is there any suggestion for that? On 12/7/11, Mahmood Naderan <[email protected]> wrote: > Hi, > While debugging O3CPU, I noticed that in this part of code > > if (!ic->isConnected()) { > Port *peer = oldCPU->getPort("icache_port")->getPeer(); > ic->setPeer(peer); > peer->setPeer(ic); > } > > if (!dc->isConnected()) { > Port *peer = oldCPU->getPort("dcache_port")->getPeer(); > dc->setPeer(peer); > peer->setPeer(dc); > } > > ic->setPeer(peer); goes to DefaultFetch<Impl>::IcachePort::setPeer(Port > *port) > but > dc->setPeer(peer); goes to LSQ<Impl>::DcachePort::setPeer(Port *port) > > Where in the code, this wiring has been defined? > > -- > // Naderan *Mahmood; > -- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
