[gem5-users] component wiring in C++ codes

[Mahmood Naderan]

Hi,
While debugging O3CPU, I noticed that in this part of code

   if (!ic->isConnected()) {
        Port *peer = oldCPU->getPort("icache_port")->getPeer();
        ic->setPeer(peer);
        peer->setPeer(ic);
    }

    if (!dc->isConnected()) {
        Port *peer = oldCPU->getPort("dcache_port")->getPeer();
        dc->setPeer(peer);
        peer->setPeer(dc);
    }

ic->setPeer(peer); goes to DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
but
dc->setPeer(peer); goes to LSQ<Impl>::DcachePort::setPeer(Port *port)

Where in the code, this wiring has been defined?

--
// Naderan *Mahmood;
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