Here we go:
in AlphaTLB.py
TLBs: 128 entries for each (D and I)
in O3CPU.py
fetchWidth = 4
decodeWidth = 4
renameWidth = 4
dispatchWidth = 6
issueWidth = 6
globalHistoryBits = 12
numPhysIntRegs = 80
numPhysFloatRegs = 72
numIQEntries = 32
numROBEntries = 80
in FuncUnitConfig.py
2x IntALU
2x IntMultDiv
2x FP_ALU (it can also handle FloatMult, FloatDiv, FloatSqrt, latencies
untouched)
0x FP_MultDiv
0x SIMD_Unit
2x RdWrPort
in FUPool.py
SIMDUnit removed
in CacheConfig.py
set fixed L2Cache size to 512 kB
set L2Bus clock to 2.4 GHz (error happens also with 1 GHz which is standard)
set fixed L1Cache size to 64 kB for Data and Instruction
in Caches.py
changed assoc of L2Cache to 16
changed latency of L2Cache to 5ns
General:
clock frequency is 2.4 GHz
started FS Mode with ALPHA ISA and -d --caches --l2cache
I think this is everything...
Best wishes
Fabian
Am 19.07.2011 23:50, schrieb Nilay:
On Tue, July 19, 2011 1:41 am, Fabian Oboril wrote:
Hey,
@Steve:
I have the newest (unstable)-release, so the bug you mentioned is not
included. However I changed a few more parameters than just the cache
size such as TLB sizes, width of issue, dispatch, ... number of
execution units and clock frequency. That is why I asked, where I can
upload my config.ini so that you can test with my settings. Putting all
the stuff here would be too much, I guess.
Can't you just post the changes that you have made?
--
Nilay
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