Hi I arrived conclusion that data is being sent to the cache which incurred the write miss form Patterson book, page 233. when a write miss occurs, coherency message makes "request data and make P (requester) the exclusive owner". could you tell me what the meaning of request data is?
On Thu, Jul 14, 2011 at 11:34 AM, Nilay <[email protected]> wrote: > On Thu, July 14, 2011 1:40 am, Hamid Reza Khaleghzadeh wrote: > > Hi > > > > I want to use MOESI-directory coherency protocol for in a 8 cores CMP. I > > have defined 4 L2's, 4 directories and 4 memory banks as following: > > > > > > Core0 Core1 Core2 Core3 Core4 Core5 Core6 > > Core7 > > |------------| |------------| > > |---------------| |---------------| > > | | > > | | > > L2 __ Dir0 L2 __ Dir1 L2 __ Dir2 > > L2 __ Dir3 > > > > > |-------------------------|--------------------------|-------------------------------| > > | > > Memory > > > > I couldn't find any information about bandwidth and latency of > > L2-directory > > link, and want to know it. Now, I have considered bandwidth and latency > L2 > > __ Dir link as L2 ----- L2 link. Is it true? > > It is certainly not true. Link latencies can be set in the python > configuration files. You would have to figure out which link connects > which network entities. I would suggest looking at the python files in > configs/ruby and in src/mem/ruby/network. > > > > > By the way, I have a question about MOESI-directory protocol. Could you > > tell > > me when a write miss occurs for an address and this address exists in > > another cache, why this data read to requested cache and then write > > operation is done? > > > How did you arrive at the conclusion that the data is being sent to the > cache which incurred the write miss? > > -- > Nilay > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Hamid Reza Khaleghzadeh
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