Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70939?usp=email )
Change subject: arch-arm: Implement FEAT_HCX
......................................................................
arch-arm: Implement FEAT_HCX
This is just making the HCRX_EL2 register read/writable;
trapping behaviour will be implemented with further extensions
Change-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70939
Maintainer: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
4 files changed, 32 insertions(+), 11 deletions(-)
Approvals:
Richard Cooper: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 4de3563..40a3a04 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -96,6 +96,8 @@
"FEAT_RNG",
"FEAT_RNG_TRAP",
"FEAT_EVT",
+ # Armv8.7
+ "FEAT_HCX",
# Armv9.2
"FEAT_SME", # Optional in Armv9.2
# Others
@@ -184,6 +186,8 @@
# Armv8.5
"FEAT_FLAGM2",
"FEAT_EVT",
+ # Armv8.7
+ "FEAT_HCX",
# Armv9.2
"FEAT_SME",
]
@@ -235,8 +239,14 @@
]
-class Armv92(Armv85):
- extensions = Armv85.extensions + ["FEAT_SME"]
+class Armv87(Armv85):
+ extensions = Armv85.extensions + [
+ "FEAT_HCX",
+ ]
+
+
+class Armv92(Armv87):
+ extensions = Armv87.extensions + ["FEAT_SME"]
class ArmAllRelease(ArmRelease):
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 69944c5..f32aa72 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1600,6 +1600,18 @@
}
Fault
+faultHcrxEL2(const MiscRegLUTEntry &entry,
+ ThreadContext *tc, const MiscRegOp64 &inst)
+{
+ const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+ if (ArmSystem::haveEL(tc, EL3) && !scr.hxen) {
+ return inst.generateTrap(EL3);
+ } else {
+ return NoFault;
+ }
+}
+
+Fault
faultZcrEL1(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
@@ -4083,6 +4095,7 @@
mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 :
0x0;
mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
+ mmfr1_el1.hcx = release->has(ArmExtension::FEAT_HCX) ? 0x1 : 0x0;
return mmfr1_el1;
}())
.faultRead(EL0, faultIdst)
@@ -4227,6 +4240,9 @@
InitReg(MISCREG_HCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HCR, MISCREG_HCR2);
+ InitReg(MISCREG_HCRX_EL2)
+ .hyp().mon()
+ .fault(EL2, faultHcrxEL2);
InitReg(MISCREG_MDCR_EL2)
.hyp().mon()
.fault(EL2, faultDebugEL2)
@@ -5654,11 +5670,6 @@
.warnNotFail()
.fault(faultUnimplemented);
- // HCX extension (unimplemented)
- InitReg(MISCREG_HCRX_EL2)
- .unimplemented()
- .warnNotFail();
-
// FGT extension (unimplemented)
InitReg(MISCREG_HFGRTR_EL2)
.unimplemented()
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 429fcb5..cb03841 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -589,6 +589,7 @@
MISCREG_SCTLR_EL2,
MISCREG_ACTLR_EL2,
MISCREG_HCR_EL2,
+ MISCREG_HCRX_EL2,
MISCREG_MDCR_EL2,
MISCREG_CPTR_EL2,
MISCREG_HSTR_EL2,
@@ -1125,9 +1126,6 @@
MISCREG_VSESR_EL2,
MISCREG_VDISR_EL2,
- // HCX extension (unimplemented)
- MISCREG_HCRX_EL2,
-
// FGT extension (unimplemented)
MISCREG_HFGRTR_EL2,
MISCREG_HFGWTR_EL2,
@@ -2272,6 +2270,7 @@
"sctlr_el2",
"actlr_el2",
"hcr_el2",
+ "hcrx_el2",
"mdcr_el2",
"cptr_el2",
"hstr_el2",
@@ -2785,7 +2784,6 @@
"disr_el1",
"vsesr_el2",
"vdisr_el2",
- "hcrx_el2",
"hfgrtr_el2",
"hfgwtr_el2",
diff --git a/src/arch/arm/regs/misc_types.hh
b/src/arch/arm/regs/misc_types.hh
index 4bb234f..00640dd 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -158,6 +158,7 @@
EndBitUnion(AA64MMFR0)
BitUnion64(AA64MMFR1)
+ Bitfield<43, 40> hcx;
Bitfield<31, 28> xnx;
Bitfield<27, 24> specsei;
Bitfield<23, 20> pan;
@@ -361,6 +362,7 @@
BitUnion64(SCR)
Bitfield<40> trndr;
+ Bitfield<38> hxen;
Bitfield<21> fien;
Bitfield<20> nmea;
Bitfield<19> ease;
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e
Gerrit-Change-Number: 70939
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
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