Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70938?usp=email )
Change subject: arch-arm: Implement FEAT_EVT
......................................................................
arch-arm: Implement FEAT_EVT
This extension is optional in Armv8.2 but mandatory since Armv8.5
We only implement this for AArch64
Change-Id: I063642ac24d27f0a81ba79b1d38f72468bb130eb
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 73 insertions(+), 18 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index b826f0d..5e45fe4 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -91,6 +91,7 @@
"FEAT_FLAGM2",
"FEAT_RNG",
"FEAT_RNG_TRAP",
+ "FEAT_EVT",
# Armv9.2
"FEAT_SME", # Optional in Armv9.2
# Others
@@ -174,6 +175,7 @@
"FEAT_IDST",
# Armv8.5
"FEAT_FLAGM2",
+ "FEAT_EVT",
# Armv9.2
"FEAT_SME",
]
@@ -217,6 +219,7 @@
"FEAT_FLAGM2",
"FEAT_RNG",
"FEAT_RNG_TRAP",
+ "FEAT_EVT",
]
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 53e9268..c8ea1f2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1445,7 +1445,8 @@
}
} else if (el2_enabled && !in_host && hcr.tpu) {
return inst.generateTrap(EL2);
- } else if (el2_enabled && !in_host && hcr.tocu) {
+ } else if (el2_enabled && !in_host &&
+ HaveExt(tc, ArmExtension::FEAT_EVT) && hcr.tocu) {
return inst.generateTrap(EL2);
} else if (el2_enabled && in_host && !sctlr2.uci) {
return inst.generateTrap(EL2);
@@ -1462,7 +1463,8 @@
const bool el2_enabled = EL2Enabled(tc);
if (el2_enabled && hcr.tpu) {
return inst.generateTrap(EL2);
- } else if (el2_enabled && hcr.tocu) {
+ } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+ hcr.tocu) {
return inst.generateTrap(EL2);
} else {
return NoFault;
@@ -1477,7 +1479,8 @@
const bool el2_enabled = EL2Enabled(tc);
if (el2_enabled && hcr.tpu) {
return inst.generateTrap(EL2);
- } else if (el2_enabled && hcr.ticab) {
+ } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+ hcr.ticab) {
return inst.generateTrap(EL2);
} else {
return NoFault;
@@ -1750,6 +1753,54 @@
}
Fault
+faultTlbiOsEL1(const MiscRegLUTEntry &entry,
+ ThreadContext *tc, const MiscRegOp64 &inst)
+{
+ const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+ const bool el2_enabled = EL2Enabled(tc);
+ if (el2_enabled && hcr.ttlb) {
+ return inst.generateTrap(EL2);
+ } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+ hcr.ttlbos) {
+ return inst.generateTrap(EL2);
+ } else {
+ return NoFault;
+ }
+}
+
+Fault
+faultTlbiIsEL1(const MiscRegLUTEntry &entry,
+ ThreadContext *tc, const MiscRegOp64 &inst)
+{
+ const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+ const bool el2_enabled = EL2Enabled(tc);
+ if (el2_enabled && hcr.ttlb) {
+ return inst.generateTrap(EL2);
+ } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+ hcr.ttlbis) {
+ return inst.generateTrap(EL2);
+ } else {
+ return NoFault;
+ }
+}
+
+Fault
+faultCacheEL1(const MiscRegLUTEntry &entry,
+ ThreadContext *tc, const MiscRegOp64 &inst)
+{
+ const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+ const bool el2_enabled = EL2Enabled(tc);
+ if (el2_enabled && hcr.tid2) {
+ return inst.generateTrap(EL2);
+ } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+ hcr.tid4) {
+ return inst.generateTrap(EL2);
+ } else {
+ return NoFault;
+ }
+}
+
+Fault
faultPauthEL1(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
@@ -4041,6 +4092,7 @@
mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 :
0x0;
mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 :
0x0;
+ mmfr2_el1.evt = release->has(ArmExtension::FEAT_EVT) ? 0x2 : 0x0;
return mmfr2_el1;
}())
.faultRead(EL0, faultIdst)
@@ -4090,11 +4142,11 @@
InitReg(MISCREG_CCSIDR_EL1)
.faultRead(EL0, faultIdst)
- .faultRead(EL1, HCR_TRAP(tid2))
+ .faultRead(EL1, faultCacheEL1)
.allPrivileges().writes(0);
InitReg(MISCREG_CLIDR_EL1)
.faultRead(EL0, faultIdst)
- .faultRead(EL1, HCR_TRAP(tid2))
+ .faultRead(EL1, faultCacheEL1)
.allPrivileges().writes(0);
InitReg(MISCREG_AIDR_EL1)
.faultRead(EL0, faultIdst)
@@ -4102,7 +4154,7 @@
.allPrivileges().writes(0);
InitReg(MISCREG_CSSELR_EL1)
.allPrivileges().exceptUserMode()
- .fault(EL1, HCR_TRAP(tid2))
+ .fault(EL1, faultCacheEL1)
.mapsTo(MISCREG_CSSELR_NS);
InitReg(MISCREG_CTR_EL0)
.faultRead(EL0, faultCtrEL0)
@@ -4471,40 +4523,40 @@
InitReg(MISCREG_AT_S1E3W_Xt)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VMALLE1OS)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiOsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1OS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiOsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1OS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiOsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1OS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiOsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1OS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiOsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1OS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiOsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VMALLE1IS)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiIsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1IS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiIsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiIsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1IS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiIsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1IS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiIsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1IS_Xt)
- .faultWrite(EL1, HCR_TRAP(ttlb))
+ .faultWrite(EL1, faultTlbiIsEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VMALLE1)
.faultWrite(EL1, HCR_TRAP(ttlb))
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I063642ac24d27f0a81ba79b1d38f72468bb130eb
Gerrit-Change-Number: 70938
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
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