Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Declare support for Armv8.2-F64MM.
......................................................................
arch-arm: Declare support for Armv8.2-F64MM.
Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-F64MM.
This indicates that all pre-requisites for Armv8.2 SVE FP64
double-precision floating-point matrix multiplication instructions
have been met.
FMMLA, and LD1RO* instructions have been implemented, as well as the
128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2.
For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)
Additional Contributors: Giacomo Travaglini
Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70729
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/process.cc
M src/arch/arm/regs/misc.cc
4 files changed, 6 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 31ecbcb..fbd93b6 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -54,6 +54,7 @@
"FEAT_RDM",
# Armv8.2
"FEAT_F32MM",
+ "FEAT_F64MM",
"FEAT_SVE",
# Armv8.3
"FEAT_FCMA",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5a7ae79..49dab3e 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -79,6 +79,7 @@
"FEAT_LVA", # Optional in Armv8.2
"FEAT_LPA", # Optional in Armv8.2
"FEAT_F32MM", # Optional in Armv8.2
+ "FEAT_F64MM", # Optional in Armv8.2
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",
@@ -165,6 +166,7 @@
"FEAT_LPA",
"FEAT_SVE",
"FEAT_F32MM",
+ "FEAT_F64MM",
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",
@@ -199,6 +201,7 @@
"FEAT_LPA",
"FEAT_SVE",
"FEAT_F32MM",
+ "FEAT_F64MM",
]
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 24e1250..be8dfff 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -322,6 +322,7 @@
const AA64ZFR0 zf_r0 = tc->readMiscReg(MISCREG_ID_AA64ZFR0_EL1);
hwcap |= (zf_r0.f32mm >= 1) ? Arm_Svef32mm : Arm_None;
+ hwcap |= (zf_r0.f64mm >= 1) ? Arm_Svef64mm : Arm_None;
return hwcap;
}
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 8925bc0..7e53e0d 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5406,6 +5406,7 @@
.reset([this](){
AA64ZFR0 zfr0_el1 = 0;
zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 :
0;
+ zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 :
0;
return zfr0_el1;
}())
.faultRead(EL0, faultIdst)
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Gerrit-Change-Number: 70729
Gerrit-PatchSet: 8
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
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