Attention is currently required from: Richard Cooper.
Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email
to review the following change.
Change subject: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT
insts.
......................................................................
arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.
Re-factored the Arm instruction decoder to add placeholders for the
SVE Integer mixed-sign DOT product instructions. This has involved
moving some existing decode helper functions.
Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
2 files changed, 128 insertions(+), 16 deletions(-)
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index e0ab5f9..4148b96 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2241,7 +2241,7 @@
}
StaticInstPtr
- decodeSveMultiplyAddUnpred(ExtMachInst machInst)
+ decodeSveIntegerDotProductUnpred(ExtMachInst machInst)
{
RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
@@ -2273,10 +2273,10 @@
}
return new Unknown64(machInst);
- } // decodeSveMultiplyAddUnpred
+ } // decodeSveIntegerDotProductUnpred
StaticInstPtr
- decodeSveMultiplyIndexed(ExtMachInst machInst)
+ decodeSveIntegerDotProductIndexed(ExtMachInst machInst)
{
RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
@@ -2310,7 +2310,59 @@
}
}
return new Unknown64(machInst);
- } // decodeSveMultiplyIndexed
+ } // decodeSveIntegerDotProductIndexed
+
+ StaticInstPtr
+ decodeSveMixedSignDotProduct(ExtMachInst machInst)
+ {
+ uint8_t size = (uint8_t) bits(machInst, 23, 22);
+ if (size != 0b10) {
+ return new Unknown64(machInst);
+ }
+
+ RegIndex zda M5_VAR_USED = (RegIndex)
+ (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn M5_VAR_USED = (RegIndex)
+ (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm M5_VAR_USED = (RegIndex)
+ (uint8_t) bits(machInst, 20, 16);
+
+ // Placeholder for SveUsdotv
+ //return SveUsdotv<int32_t, uint8_t, int8_t>(machInst, zda, zn,
zm);
+ return new Unknown64(machInst);
+ } // decodeSveMixedSignDotProduct
+
+ StaticInstPtr
+ decodeSveMixedSignDotProductIndexed(ExtMachInst machInst)
+ {
+ uint8_t size = (uint8_t) bits(machInst, 23, 22);
+ if (size != 0b10) {
+ return new Unknown64(machInst);
+ }
+
+ RegIndex zda M5_VAR_USED = (RegIndex)
+ (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn M5_VAR_USED = (RegIndex)
+ (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm M5_VAR_USED = (RegIndex)
+ (uint8_t) bits(machInst, 18, 16);
+ uint8_t i2 M5_VAR_USED = (uint8_t) bits(machInst, 20, 19);
+
+ uint8_t usig = (uint8_t) bits(machInst, 10);
+
+ if (usig) {
+ // Placeholder for SveSudoti
+ //return SveSudoti<int32_t, int8_t, uint8_t>
+ // (machInst, zda, zn, zm, i2);
+ return new Unknown64(machInst);
+ } else {
+ // Placeholder for SveUsdoti
+ //return SveUsdoti<int32_t, uint8_t, int8_t>
+ // (machInst, zda, zn, zm, i2);
+ return new Unknown64(machInst);
+ }
+
+ } // decodeSveMixedSignDotProductIndexed
StaticInstPtr
decodeSveFpFastReduc(ExtMachInst machInst)
@@ -3805,6 +3857,43 @@
return new Unknown64(machInst);
} // decodeSveMisc
+ StaticInstPtr
+ decodeSveIntegerMulAddUnpred(ExtMachInst machInst)
+ {
+ uint8_t op1 = (uint8_t) bits(machInst, 13, 11);
+ if (bits(machInst, 14) == 0b0) {
+ if (op1 == 0b000) {
+ return decodeSveIntegerDotProductUnpred(machInst);
+ } else {
+ return new Unknown64(machInst);
+ }
+ } else {
+ if (op1 == 0b111 &&
+ bits(machInst, 10) == 0b0) {
+ return decodeSveMixedSignDotProduct(machInst);
+ } else {
+ return new Unknown64(machInst);
+ }
+ }
+ }
+
+ StaticInstPtr
+ decodeSveMultiplyIndexed(ExtMachInst machInst)
+ {
+ if (bits(machInst, 15, 13) == 0b000) {
+ switch (bits(machInst, 12, 11)) {
+ case 0b00:
+ return decodeSveIntegerDotProductIndexed(machInst);
+ case 0b11:
+ return decodeSveMixedSignDotProductIndexed(machInst);
+ default:
+ return new Unknown64(machInst);
+ }
+ } else {
+ return new Unknown64(machInst);
+ }
+ return new Unknown64(machInst);
+ }
} // namespace Aarch64
}};
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa
b/src/arch/arm/isa/formats/sve_top_level.isa
index 0699637..d4c2a13 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -71,8 +71,10 @@
StaticInstPtr decodeSveIntWideImmUnpred(ExtMachInst machInst);
StaticInstPtr decodeSveClamp(ExtMachInst machInst);
- StaticInstPtr decodeSveMultiplyAddUnpred(ExtMachInst machInst);
- StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst);
+ StaticInstPtr decodeSveIntegerDotProductUnpred(ExtMachInst machInst);
+ StaticInstPtr decodeSveIntegerDotProductIndexed(ExtMachInst machInst);
+ StaticInstPtr decodeSveMixedSignDotProduct(ExtMachInst machInst);
+ StaticInstPtr decodeSveMixedSignDotProductIndexed(ExtMachInst
machInst);
StaticInstPtr decodeSveFpFastReduc(ExtMachInst machInst);
StaticInstPtr decodeSveFpUnaryUnpred(ExtMachInst machInst);
@@ -96,6 +98,8 @@
StaticInstPtr decodeSveMemStore(ExtMachInst machInst);
StaticInstPtr decodeSveMisc(ExtMachInst machInst);
+ StaticInstPtr decodeSveIntegerMulAddUnpred(ExtMachInst machInst);
+ StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst);
}
}};
@@ -107,10 +111,31 @@
decodeSveInt(ExtMachInst machInst)
{
if (bits(machInst, 31, 29) == 0b010) {
- if (bits(machInst, 24) == 0b1 &&
- bits(machInst, 21) == 0b0 &&
- bits(machInst, 15, 14)==0b10) {
- return decodeSveMisc(machInst);
+ uint8_t op1 = bits(machInst, 24, 23);
+ switch (op1) {
+ case 0b00:
+ case 0b01:
+ if (bits(machInst, 21) == 0b0) {
+ if (bits(machInst, 15) == 0b0) {
+ return decodeSveIntegerMulAddUnpred(machInst);
+ } else {
+ return new Unknown64(machInst);
+ }
+ } else {
+ return decodeSveMultiplyIndexed(machInst);
+ }
+ break;
+ case 0b10:
+ case 0b11:
+ if (bits(machInst, 21) == 0b0 &&
+ bits(machInst, 15, 14) == 0b10) {
+ return decodeSveMisc(machInst);
+ } else {
+ return new Unknown64(machInst);
+ }
+ break;
+ default:
+ return new Unknown64(machInst);
}
}
@@ -130,11 +155,10 @@
bits(machInst, 13);
switch (b_15_13) {
case 0x0:
- if (bits(machInst, 30)) {
- return decodeSveMultiplyAddUnpred(machInst);
- } else {
+ if (!bits(machInst, 30)) {
return decodeSveIntArithBinPred(machInst);
}
+ break;
case 0x1:
return decodeSveIntReduc(machInst);
case 0x2:
@@ -155,12 +179,11 @@
if (b_13) {
return decodeSveIntLogUnpred(machInst);
} else {
- if (bits(machInst, 30)) {
- return decodeSveMultiplyIndexed(machInst);
- } else {
+ if (!bits(machInst, 30)) {
return decodeSveIntArithUnpred(machInst);
}
}
+ break;
case 0x1:
if (b_13) {
return new Unknown64(machInst);
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218
Gerrit-Change-Number: 70731
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Attention: Richard Cooper <richard.coo...@arm.com>
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