Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70117?usp=email )
Change subject: mem: Fix SW prefetch asynchronous handling
......................................................................
mem: Fix SW prefetch asynchronous handling
SoftPFResp was tagged with "HasData", but this wasn't true in case the
(L1D) cache missed. In this case, the packet was copied, and the original
was returned immediately, asynchronously, without data. The idea is that
the CPU doesn't need the data anyway, but this copies uninitialized data
into any concurrent functional reads with an overlapping address range.
This commit removes the HasData flag, and makes the cache not add data
even if it is available (on a hit).
Note: SWPrefetch requests are turned into Read(Shared|Ex)Reqs before
forwarding to further away caches, so the data field was always ignored.
Change-Id: I56c3452d86f08a31fb8b5303ba7084ebe10655cd
---
M src/mem/cache/base.cc
M src/mem/packet.cc
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 87c44ce..d954f01 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2018-2019 ARM Limited
+ * Copyright (c) 2012-2013, 2018-2019, 2023 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -1149,6 +1149,10 @@
// this cache before knowing the store will fail.
blk->setCoherenceBits(CacheBlk::DirtyBit);
DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__,
pkt->print());
+ } else if (pkt->cmd.isSWPrefetch()) {
+ // Nothing to do. SW prefetches don't carry data in the response,
as
+ // the CPU will ignore it anyway.
+ assert(!pkt->hasRespData());
} else if (pkt->isRead()) {
if (pkt->isLLSC()) {
blk->trackLoadLocked(pkt);
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 31dc330..d48c8b7 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2019, 2021 ARM Limited
+ * Copyright (c) 2011-2019, 2021, 2023 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -111,7 +111,7 @@
{ {IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache},
HardPFResp, "HardPFReq" },
/* SoftPFResp */
- { {IsRead, IsResponse, IsSWPrefetch, HasData},
InvalidCmd, "SoftPFResp" },
+ { {IsRead, IsResponse, IsSWPrefetch}, InvalidCmd, "SoftPFResp" },
/* HardPFResp */
{ {IsRead, IsResponse, IsHWPrefetch, HasData},
InvalidCmd, "HardPFResp" },
/* WriteLineReq */
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I56c3452d86f08a31fb8b5303ba7084ebe10655cd
Gerrit-Change-Number: 70117
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
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