Attention is currently required from: Bobby Bruce, Yu-hsin Wang.
Hello kokoro, Bobby Bruce, Yu-hsin Wang,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70097?usp=email
to review the following change.
Change subject: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"
......................................................................
Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"
This reverts commit 083566d0c82d2610b246b0b5ad903766e336ac31.
Reason for revert: Remove the additional RV32 tests
This is early version support RV32 instruction tests. To enable run RV32
instruction. We select Riscv32AtomicSimpleCPU, Riscv32TimingSimpleCPU and
so on to run RV32 instruction. We should directly set isa feature of
RiscvCPU to run RV32 instruction
Change-Id: I51b744e9d827adfabc2a7c222ab3801d454601d1
---
M tests/gem5/asmtest/tests.py
M tests/gem5/configs/simple_binary_run.py
2 files changed, 160 insertions(+), 211 deletions(-)
diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index 0ddffb2..b2a5992 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -34,159 +34,156 @@
# The following lists the RISCV binaries. Those commented out presently
result
# in a test failure. This is outlined in the following Jira issue:
# https://gem5.atlassian.net/browse/GEM5-496
-binary_configs = (
- ("rv{}samt-ps-sysclone_d", (64,)),
- ("rv{}samt-ps-sysfutex1_d", (64,)),
+binaries = (
+ "rv64samt-ps-sysclone_d",
+ "rv64samt-ps-sysfutex1_d",
# 'rv64samt-ps-sysfutex2_d',
- ("rv{}samt-ps-sysfutex3_d", (64,)),
+ "rv64samt-ps-sysfutex3_d",
# 'rv64samt-ps-sysfutex_d',
- ("rv{}ua-ps-amoadd_d", (64,)),
- ("rv{}ua-ps-amoadd_w", (32, 64)),
- ("rv{}ua-ps-amoand_d", (64,)),
- ("rv{}ua-ps-amoand_w", (32, 64)),
- ("rv{}ua-ps-amomax_d", (64,)),
- ("rv{}ua-ps-amomax_w", (32, 64)),
- ("rv{}ua-ps-amomaxu_d", (64,)),
- ("rv{}ua-ps-amomaxu_w", (32, 64)),
- ("rv{}ua-ps-amomin_d", (64,)),
- ("rv{}ua-ps-amomin_w", (32, 64)),
- ("rv{}ua-ps-amominu_d", (64,)),
- ("rv{}ua-ps-amominu_w", (32, 64)),
- ("rv{}ua-ps-amoor_d", (64,)),
- ("rv{}ua-ps-amoor_w", (32, 64)),
- ("rv{}ua-ps-amoswap_d", (64,)),
- ("rv{}ua-ps-amoswap_w", (32, 64)),
- ("rv{}ua-ps-amoxor_d", (64,)),
- ("rv{}ua-ps-amoxor_w", (32, 64)),
- ("rv{}ua-ps-lrsc", (32, 64)),
- ("rv{}uamt-ps-amoadd_d", (64,)),
- ("rv{}uamt-ps-amoand_d", (64,)),
- ("rv{}uamt-ps-amomax_d", (64,)),
- ("rv{}uamt-ps-amomaxu_d", (64,)),
- ("rv{}uamt-ps-amomin_d", (64,)),
- ("rv{}uamt-ps-amominu_d", (64,)),
- ("rv{}uamt-ps-amoor_d", (64,)),
- ("rv{}uamt-ps-amoswap_d", (64,)),
- ("rv{}uamt-ps-amoxor_d", (64,)),
- ("rv{}uamt-ps-lrsc_d", (64,)),
- ("rv{}uamt-ps-amoadd_w", (32,)),
- ("rv{}uamt-ps-amoand_w", (32,)),
- ("rv{}uamt-ps-amomax_w", (32,)),
- ("rv{}uamt-ps-amomaxu_w", (32,)),
- ("rv{}uamt-ps-amomin_w", (32,)),
- ("rv{}uamt-ps-amominu_w", (32,)),
- ("rv{}uamt-ps-amoor_w", (32,)),
- ("rv{}uamt-ps-amoswap_w", (32,)),
- ("rv{}uamt-ps-amoxor_w", (32,)),
- ("rv{}uamt-ps-lrsc_w", (32,)),
- ("rv{}ud-ps-fadd", (32, 64)),
- ("rv{}ud-ps-fclass", (32, 64)),
- ("rv{}ud-ps-fcmp", (32, 64)),
- ("rv{}ud-ps-fcvt", (32, 64)),
- ("rv{}ud-ps-fcvt_w", (32, 64)),
- ("rv{}ud-ps-fdiv", (32, 64)),
- ("rv{}ud-ps-fmadd", (32, 64)),
- ("rv{}ud-ps-fmin", (32, 64)),
- ("rv{}ud-ps-ldst", (32, 64)),
- ("rv{}ud-ps-move", (64,)),
- ("rv{}ud-ps-recoding", (32, 64)),
- ("rv{}ud-ps-structural", (64,)),
- ("rv{}uf-ps-fadd", (32, 64)),
- ("rv{}uf-ps-fclass", (32, 64)),
- ("rv{}uf-ps-fcmp", (32, 64)),
- ("rv{}uf-ps-fcvt", (32, 64)),
- ("rv{}uf-ps-fcvt_w", (32, 64)),
- ("rv{}uf-ps-fdiv", (32, 64)),
- ("rv{}uf-ps-fmadd", (32, 64)),
- ("rv{}uf-ps-fmin", (32, 64)),
- ("rv{}uf-ps-ldst", (32, 64)),
- ("rv{}uf-ps-move", (32, 64)),
- ("rv{}uf-ps-recoding", (32, 64)),
- ("rv{}ui-ps-add", (32, 64)),
- ("rv{}ui-ps-addi", (32, 64)),
- ("rv{}ui-ps-addiw", (64,)),
- ("rv{}ui-ps-addw", (64,)),
- ("rv{}ui-ps-and", (32, 64)),
- ("rv{}ui-ps-andi", (32, 64)),
- ("rv{}ui-ps-auipc", (32, 64)),
- ("rv{}ui-ps-beq", (32, 64)),
- ("rv{}ui-ps-bge", (32, 64)),
- ("rv{}ui-ps-bgeu", (32, 64)),
- ("rv{}ui-ps-blt", (32, 64)),
- ("rv{}ui-ps-bltu", (32, 64)),
- ("rv{}ui-ps-bne", (32, 64)),
- ("rv{}ui-ps-fence_i", (32, 64)),
- ("rv{}ui-ps-jal", (32, 64)),
- ("rv{}ui-ps-jalr", (32, 64)),
- ("rv{}ui-ps-lb", (32, 64)),
- ("rv{}ui-ps-lbu", (32, 64)),
- ("rv{}ui-ps-ld", (64,)),
- ("rv{}ui-ps-lh", (32, 64)),
- ("rv{}ui-ps-lhu", (32, 64)),
- ("rv{}ui-ps-lui", (32, 64)),
- ("rv{}ui-ps-lw", (32, 64)),
- ("rv{}ui-ps-lwu", (64,)),
- ("rv{}ui-ps-or", (32, 64)),
- ("rv{}ui-ps-ori", (32, 64)),
- ("rv{}ui-ps-sb", (32, 64)),
- ("rv{}ui-ps-sd", (64,)),
- ("rv{}ui-ps-sh", (32, 64)),
- ("rv{}ui-ps-simple", (32, 64)),
- ("rv{}ui-ps-sll", (32, 64)),
- ("rv{}ui-ps-slli", (32, 64)),
- ("rv{}ui-ps-slliw", (64,)),
- ("rv{}ui-ps-sllw", (64,)),
- ("rv{}ui-ps-slt", (32, 64)),
- ("rv{}ui-ps-slti", (32, 64)),
- ("rv{}ui-ps-sltiu", (32, 64)),
- ("rv{}ui-ps-sltu", (32, 64)),
- ("rv{}ui-ps-sra", (32, 64)),
- ("rv{}ui-ps-srai", (32, 64)),
- ("rv{}ui-ps-sraiw", (64,)),
- ("rv{}ui-ps-sraw", (64,)),
- ("rv{}ui-ps-srl", (32, 64)),
- ("rv{}ui-ps-srli", (32, 64)),
- ("rv{}ui-ps-srliw", (64,)),
- ("rv{}ui-ps-srlw", (64,)),
- ("rv{}ui-ps-sub", (32, 64)),
- ("rv{}ui-ps-subw", (64,)),
- ("rv{}ui-ps-sw", (32, 64)),
- ("rv{}ui-ps-xor", (32, 64)),
- ("rv{}ui-ps-xori", (32, 64)),
- ("rv{}um-ps-div", (32, 64)),
- ("rv{}um-ps-divu", (32, 64)),
- ("rv{}um-ps-divuw", (64,)),
- ("rv{}um-ps-divw", (64,)),
- ("rv{}um-ps-mul", (32, 64)),
- ("rv{}um-ps-mulh", (32, 64)),
- ("rv{}um-ps-mulhsu", (32, 64)),
- ("rv{}um-ps-mulhu", (32, 64)),
- ("rv{}um-ps-mulw", (64,)),
- ("rv{}um-ps-rem", (32, 64)),
- ("rv{}um-ps-remu", (32, 64)),
- ("rv{}um-ps-remuw", (64,)),
- ("rv{}um-ps-remw", (64,)),
- ("rv{}uzfh-ps-fadd", (32, 64)),
- ("rv{}uzfh-ps-fclass", (32, 64)),
- ("rv{}uzfh-ps-fcmp", (32, 64)),
- ("rv{}uzfh-ps-fcvt", (32, 64)),
- ("rv{}uzfh-ps-fcvt_w", (32, 64)),
- ("rv{}uzfh-ps-fdiv", (32, 64)),
- ("rv{}uzfh-ps-fmadd", (32, 64)),
- ("rv{}uzfh-ps-fmin", (32, 64)),
- ("rv{}uzfh-ps-ldst", (32, 64)),
- ("rv{}uzfh-ps-move", (32, 64)),
- ("rv{}uzfh-ps-recoding", (32, 64)),
+ "rv64ua-ps-amoadd_d",
+ "rv64ua-ps-amoadd_w",
+ "rv64ua-ps-amoand_d",
+ "rv64ua-ps-amoand_w",
+ "rv64ua-ps-amomax_d",
+ "rv64ua-ps-amomax_w",
+ "rv64ua-ps-amomaxu_d",
+ "rv64ua-ps-amomaxu_w",
+ "rv64ua-ps-amomin_d",
+ "rv64ua-ps-amomin_w",
+ "rv64ua-ps-amominu_d",
+ "rv64ua-ps-amominu_w",
+ "rv64ua-ps-amoor_d",
+ "rv64ua-ps-amoor_w",
+ "rv64ua-ps-amoswap_d",
+ "rv64ua-ps-amoswap_w",
+ "rv64ua-ps-amoxor_d",
+ "rv64ua-ps-amoxor_w",
+ "rv64ua-ps-lrsc",
+ "rv64uamt-ps-amoadd_d",
+ "rv64uamt-ps-amoand_d",
+ "rv64uamt-ps-amomax_d",
+ "rv64uamt-ps-amomaxu_d",
+ "rv64uamt-ps-amomin_d",
+ "rv64uamt-ps-amominu_d",
+ "rv64uamt-ps-amoor_d",
+ "rv64uamt-ps-amoswap_d",
+ "rv64uamt-ps-amoxor_d",
+ "rv64uamt-ps-lrsc_d",
+ "rv64ud-ps-fadd",
+ "rv64ud-ps-fclass",
+ "rv64ud-ps-fcmp",
+ "rv64ud-ps-fcvt",
+ "rv64ud-ps-fcvt_w",
+ "rv64ud-ps-fdiv",
+ "rv64ud-ps-fmadd",
+ "rv64ud-ps-fmin",
+ "rv64ud-ps-ldst",
+ "rv64ud-ps-move",
+ "rv64ud-ps-recoding",
+ "rv64ud-ps-structural",
+ "rv64uf-ps-fadd",
+ "rv64uf-ps-fclass",
+ "rv64uf-ps-fcmp",
+ "rv64uf-ps-fcvt",
+ "rv64uf-ps-fcvt_w",
+ "rv64uf-ps-fdiv",
+ "rv64uf-ps-fmadd",
+ "rv64uf-ps-fmin",
+ "rv64uf-ps-ldst",
+ "rv64uf-ps-move",
+ "rv64uf-ps-recoding",
+ "rv64ui-ps-add",
+ "rv64ui-ps-addi",
+ "rv64ui-ps-addiw",
+ "rv64ui-ps-addw",
+ "rv64ui-ps-and",
+ "rv64ui-ps-andi",
+ "rv64ui-ps-auipc",
+ "rv64ui-ps-beq",
+ "rv64ui-ps-bge",
+ "rv64ui-ps-bgeu",
+ "rv64ui-ps-blt",
+ "rv64ui-ps-bltu",
+ "rv64ui-ps-bne",
+ "rv64ui-ps-fence_i",
+ "rv64ui-ps-jal",
+ "rv64ui-ps-jalr",
+ "rv64ui-ps-lb",
+ "rv64ui-ps-lbu",
+ "rv64ui-ps-ld",
+ "rv64ui-ps-lh",
+ "rv64ui-ps-lhu",
+ "rv64ui-ps-lui",
+ "rv64ui-ps-lw",
+ "rv64ui-ps-lwu",
+ "rv64ui-ps-or",
+ "rv64ui-ps-ori",
+ "rv64ui-ps-sb",
+ "rv64ui-ps-sd",
+ "rv64ui-ps-sh",
+ "rv64ui-ps-simple",
+ "rv64ui-ps-sll",
+ "rv64ui-ps-slli",
+ "rv64ui-ps-slliw",
+ "rv64ui-ps-sllw",
+ "rv64ui-ps-slt",
+ "rv64ui-ps-slti",
+ "rv64ui-ps-sltiu",
+ "rv64ui-ps-sltu",
+ "rv64ui-ps-sra",
+ "rv64ui-ps-srai",
+ "rv64ui-ps-sraiw",
+ "rv64ui-ps-sraw",
+ "rv64ui-ps-srl",
+ "rv64ui-ps-srli",
+ "rv64ui-ps-srliw",
+ "rv64ui-ps-srlw",
+ "rv64ui-ps-sub",
+ "rv64ui-ps-subw",
+ "rv64ui-ps-sw",
+ "rv64ui-ps-xor",
+ "rv64ui-ps-xori",
+ "rv64um-ps-div",
+ "rv64um-ps-divu",
+ "rv64um-ps-divuw",
+ "rv64um-ps-divw",
+ "rv64um-ps-mul",
+ "rv64um-ps-mulh",
+ "rv64um-ps-mulhsu",
+ "rv64um-ps-mulhu",
+ "rv64um-ps-mulw",
+ "rv64um-ps-rem",
+ "rv64um-ps-remu",
+ "rv64um-ps-remuw",
+ "rv64um-ps-remw",
+ "rv64uzfh-ps-fadd",
+ "rv64uzfh-ps-fclass",
+ "rv64uzfh-ps-fcmp",
+ "rv64uzfh-ps-fcvt",
+ "rv64uzfh-ps-fcvt_w",
+ "rv64uzfh-ps-fdiv",
+ "rv64uzfh-ps-fmadd",
+ "rv64uzfh-ps-fmin",
+ "rv64uzfh-ps-ldst",
+ "rv64uzfh-ps-move",
+ "rv64uzfh-ps-recoding",
)
cpu_types = ("atomic", "timing", "minor", "o3")
for cpu_type in cpu_types:
- for cfg in binary_configs:
- template_bin, all_bits = cfg
- for bits in all_bits:
- binary = template_bin.format(bits)
- config_args = [
+ for binary in binaries:
+ gem5_verify_config(
+ name=f"asm-riscv-{binary}-{cpu_type}",
+ verifiers=(),
+ config=joinpath(
+ config.base_dir,
+ "tests",
+ "gem5",
+ "configs",
+ "simple_binary_run.py",
+ ),
+ config_args=[
binary,
cpu_type,
"riscv",
@@ -194,20 +191,7 @@
"4",
"--resource-directory",
resource_path,
- ]
- if bits == 32:
- config_args.extend(["-b", "--riscv-32bits"])
- gem5_verify_config(
- name=f"asm-riscv-{binary}-{cpu_type}",
- verifiers=(),
- config=joinpath(
- config.base_dir,
- "tests",
- "gem5",
- "configs",
- "simple_binary_run.py",
- ),
- config_args=config_args,
- valid_isas=(constants.all_compiled_tag,),
- valid_hosts=constants.supported_hosts,
- )
+ ],
+ valid_isas=(constants.all_compiled_tag,),
+ valid_hosts=constants.supported_hosts,
+ )
diff --git a/tests/gem5/configs/simple_binary_run.py
b/tests/gem5/configs/simple_binary_run.py
index fbb0313..d69e1a1 100644
--- a/tests/gem5/configs/simple_binary_run.py
+++ b/tests/gem5/configs/simple_binary_run.py
@@ -1,5 +1,4 @@
# Copyright (c) 2021 The Regents of the University of California
-# Copyright (c) 2022 Google Inc
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -45,23 +44,12 @@
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
-from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
-
-from m5.util import fatal
+from gem5.isas import get_isa_from_str, get_isas_str_set
import argparse
-import importlib
from python.gem5.components.processors.base_cpu_core import BaseCPUCore
-cpu_types_string_map = {
- CPUTypes.ATOMIC: "AtomicSimpleCPU",
- CPUTypes.O3: "O3CPU",
- CPUTypes.TIMING: "TimingSimpleCPU",
- CPUTypes.KVM: "KvmCPU",
- CPUTypes.MINOR: "MinorCPU",
-}
-
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."
)
@@ -86,12 +74,6 @@
)
parser.add_argument(
- "--riscv-32bits",
- action="store_true",
- help="Use 32 bits core of Riscv CPU",
-)
-
-parser.add_argument(
"-r",
"--resource-directory",
type=str,
@@ -123,43 +105,26 @@
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
-isa_enum = get_isa_from_str(args.isa)
-cpu_enum = get_cpu_type_from_str(args.cpu)
-
-if isa_enum == ISA.RISCV and args.riscv_32bits and not
args.base_cpu_processor:
- fatal("To use Riscv 32 CPU, the base_cpu_processor must be specify!")
-
if args.base_cpu_processor:
-
- if isa_enum == ISA.RISCV and args.riscv_32bits:
- m5_objects = importlib.import_module("m5.objects")
- cpu_class = getattr(
- m5_objects, f"Riscv32{cpu_types_string_map[cpu_enum]}"
+ cores = [
+ BaseCPUCore(
+ core=SimpleCore.cpu_simobject_factory(
+ cpu_type=get_cpu_type_from_str(args.cpu),
+ isa=get_isa_from_str(args.isa),
+ core_id=i,
+ ),
+ isa=get_isa_from_str(args.isa),
)
- cores = [
- BaseCPUCore(core=cpu_class(cpu_id=i), isa=isa_enum)
- for i in range(args.num_cores)
- ]
- else:
- cores = [
- BaseCPUCore(
- core=SimpleCore.cpu_simobject_factory(
- cpu_type=cpu_enum,
- isa=isa_enum,
- core_id=i,
- ),
- isa=isa_enum,
- )
- for i in range(args.num_cores)
- ]
+ for i in range(args.num_cores)
+ ]
processor = BaseCPUProcessor(
cores=cores,
)
else:
processor = SimpleProcessor(
- cpu_type=cpu_enum,
- isa=isa_enum,
+ cpu_type=get_cpu_type_from_str(args.cpu),
+ isa=get_isa_from_str(args.isa),
num_cores=args.num_cores,
)
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I51b744e9d827adfabc2a7c222ab3801d454601d1
Gerrit-Change-Number: 70097
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Earl Ou <shunhsin...@google.com>
Gerrit-CC: Jui-min Lee <f...@google.com>
Gerrit-Attention: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Attention: Yu-hsin Wang <yuhsi...@google.com>
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