Tom Rollet has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68799?usp=email )
Change subject: stdlib: add custom import of cache models
......................................................................
stdlib: add custom import of cache models
The user can now pass, to the cache hierarchy, custom cache objects
that he wants to use.
In the case where no cache is provided, the corresponding cache from the
cachehierarchies/classic/cache/ directory will be used.
Change-Id: I552851c36a43744561d764b431004b58955c7d8d
---
M
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
M
src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
3 files changed, 64 insertions(+), 15 deletions(-)
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
index ea2a8e8..e67a848 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
@@ -65,15 +65,29 @@
l1i_size: Optional[str] = None,
l1d_assoc: Optional[int] = None,
l1i_assoc: Optional[int] = None,
+ l1i: Optional[Cache] = None,
+ l1d: Optional[Cache] = None,
membus: BaseXBar = _get_default_membus.__func__(),
) -> None:
"""
:param l1d_size: The size of the L1 Data Cache (e.g., "32kB").
+ :type l1d_size: str
:param l1i_size: The size of the L1 Instruction Cache
(e.g., "32kB").
+ :type l1i_size: str
+
+ :param l2_size: The size of the L2 Cache (e.g., "256kB").
+ :type l2_size: str
+
+ :param l1i: A cache to use as l1i
+ :type l1i: Cache
+
+ :param l1d: A cache to use as l1d
+ :type l1d: Cache
:param membus: The memory bus. This parameter is optional
parameter and
will default to a 64 bit width SystemXBar is not specified.
+ :type membus: BaseXBar
"""
AbstractClassicCacheHierarchy.__init__(self=self)
@@ -84,6 +98,9 @@
self._l1i_assoc = l1i_assoc
self._l1d_assoc = l1d_assoc
+ self._l1i = l1i if l1i else L1ICache
+ self._l1d = l1d if l1d else L1DCache
+
@overrides(AbstractClassicCacheHierarchy)
def get_mem_side_port(self) -> Port:
return self.membus.mem_side_ports
@@ -104,13 +121,13 @@
_num_cores = board.get_processor().get_num_cores()
self.l1icaches = add_caches(
- cache=L1ICache,
+ cache=self._l1i,
num_caches=_num_cores,
size=self._l1i_size,
assoc=self._l1i_assoc,
)
self.l1dcaches = add_caches(
- cache=L1DCache,
+ cache=self._l1d,
num_caches=_num_cores,
size=self._l1d_size,
assoc=self._l1d_assoc,
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index 80319e1..4762095 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -71,24 +71,32 @@
l1d_assoc: Optional[int] = None,
l1i_assoc: Optional[int] = None,
l2_assoc: Optional[int] = None,
+ l1i: Optional[Cache] = None,
+ l1d: Optional[Cache] = None,
+ l2: Optional[Cache] = None,
membus: BaseXBar = _get_default_membus.__func__(),
) -> None:
"""
:param l1d_size: The size of the L1 Data Cache (e.g., "32kB").
-
:type l1d_size: str
:param l1i_size: The size of the L1 Instruction Cache
(e.g., "32kB").
-
:type l1i_size: str
:param l2_size: The size of the L2 Cache (e.g., "256kB").
-
:type l2_size: str
+ :param l1i: A cache to use as l1i
+ :type l1i: Cache
+
+ :param l1d: A cache to use as l1d
+ :type l1d: Cache
+
+ :param l2: A cache to use as l2
+ :type l2: Cache
+
:param membus: The memory bus. This parameter is optional
parameter and
will default to a 64 bit width SystemXBar is not specified.
-
:type membus: BaseXBar
"""
@@ -101,6 +109,10 @@
self._l1d_assoc = l1d_assoc
self._l2_assoc = l2_assoc
+ self._l1i = l1i if l1i else L1ICache
+ self._l1d = l1d if l1d else L1DCache
+ self._l2 = l2 if l2 else L2Cache
+
self.membus = membus
@overrides(AbstractClassicCacheHierarchy)
@@ -123,14 +135,14 @@
_num_cores = board.get_processor().get_num_cores()
self.l1icaches = add_caches(
- cache=L1ICache,
+ cache=self._l1i,
num_caches=_num_cores,
size=self._l1i_size,
assoc=self._l1i_assoc,
)
self.l1dcaches = add_caches(
- cache=L1DCache,
+ cache=self._l1d,
num_caches=_num_cores,
size=self._l1d_size,
assoc=self._l1d_assoc,
@@ -139,7 +151,7 @@
self.l2buses = add_buses(bus=L2XBar, num_buses=_num_cores)
self.l2caches = add_caches(
- cache=L2Cache,
+ cache=self._l2,
num_caches=_num_cores,
size=self._l2_size,
assoc=self._l2_assoc,
diff --git
a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
index c7f3fee..4665aff 100644
---
a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
+++
b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
@@ -71,17 +71,33 @@
l1d_assoc: Optional[int] = None,
l1i_assoc: Optional[int] = None,
l2_assoc: Optional[int] = None,
+ l1i: Optional[Cache] = None,
+ l1d: Optional[Cache] = None,
+ l2: Optional[Cache] = None,
membus: BaseXBar = _get_default_membus.__func__(),
) -> None:
"""
:param l1d_size: The size of the L1 Data Cache (e.g., "32kB").
+ :type l1d_size: str
+
:param l1i_size: The size of the L1 Instruction Cache
(e.g., "32kB").
+ :type l1i_size: str
+
:param l2_size: The size of the L2 Cache (e.g., "256kB").
- :param l1d_assoc: The associativity of the L1 Data Cache.
- :param l1i_assoc: The associativity of the L1 Instruction Cache.
- :param l2_assoc: The associativity of the L2 Cache.
+ :type l2_size: str
+
+ :param l1i: A cache to use as l1i
+ :type l1i: Cache
+
+ :param l1d: A cache to use as l1d
+ :type l1d: Cache
+
+ :param l2: A cache to use as l2
+ :type l2: Cache
+
:param membus: The memory bus. This parameter is optional
parameter and
will default to a 64 bit width SystemXBar is not specified.
+ :type membus: BaseXBar
"""
AbstractClassicCacheHierarchy.__init__(self=self)
@@ -93,6 +109,10 @@
self._l1d_assoc = l1d_assoc
self._l2_assoc = l2_assoc
+ self._l1i = l1i if l1i else L1ICache
+ self._l1d = l1d if l1d else L1DCache
+ self._l2 = l2 if l2 else L2Cache
+
self.membus = membus
@overrides(AbstractClassicCacheHierarchy)
@@ -115,14 +135,14 @@
_num_cores = board.get_processor().get_num_cores()
self.l1icaches = add_caches(
- cache=L1ICache,
+ cache=self._l1i,
num_caches=_num_cores,
size=self._l1i_size,
assoc=self._l1i_assoc,
)
self.l1dcaches = add_caches(
- cache=L1DCache,
+ cache=self._l1d,
num_caches=_num_cores,
size=self._l1d_size,
assoc=self._l1d_assoc,
@@ -131,7 +151,7 @@
self.l2bus = add_buses(bus=L2XBar, num_buses=1)[0]
self.l2cache = add_caches(
- cache=L2Cache,
+ cache=self._l2,
num_caches=1,
size=self._l2_size,
assoc=self._l2_assoc,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I552851c36a43744561d764b431004b58955c7d8d
Gerrit-Change-Number: 68799
Gerrit-PatchSet: 1
Gerrit-Owner: Tom Rollet <tom.rol...@huawei.com>
Gerrit-MessageType: newchange
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