Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44969 )
Change subject: arch-arm: Stop using the DmaPort in the TableWalker
......................................................................
arch-arm: Stop using the DmaPort in the TableWalker
Using a custom TableWalker::Port subclassing MemPort
Change-Id: I1a13779512c2862da55ef4d2dec28bf47f12eb47
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
5 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index a741537..bd79ce3 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -131,7 +131,7 @@
}
if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
- parent.getDMAPort().dmaAction(
+ parent.getMemPort().walk(
MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
tc->getCpuPtr()->clockPeriod(), req->getFlags());
} else {
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index c416b15..8e75893 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -39,8 +39,8 @@
#define __ARCH_ARM_STAGE2_MMU_HH__
#include "arch/arm/faults.hh"
+#include "arch/arm/table_walker.hh"
#include "arch/arm/tlb.hh"
-#include "dev/dma_device.hh"
#include "mem/request.hh"
#include "params/ArmStage2MMU.hh"
#include "sim/eventq.hh"
@@ -57,7 +57,7 @@
protected:
/** Port to issue translation requests from */
- DmaPort port;
+ TableWalker::Port port;
/** Request id for requests generated by this MMU */
RequestorID requestorId;
@@ -109,7 +109,7 @@
* is used by the two table walkers, and is exposed externally and
* connected through the stage-one table walker.
*/
- DmaPort& getDMAPort() { return port; }
+ TableWalker::Port& getMemPort() { return port; }
Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
uint8_t *data, int numBytes, Request::Flags flags, bool
isFunctional);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 82a9570..2c45a5d 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2019 ARM Limited
+ * Copyright (c) 2010, 2012-2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -101,7 +101,7 @@
TableWalker::setMMU(Stage2MMU *m, RequestorID requestor_id)
{
stage2Mmu = m;
- port = &m->getDMAPort();
+ port = &m->getMemPort();
requestorId = requestor_id;
}
@@ -113,7 +113,7 @@
fatal_if(!tlb, "Table walker must have a valid TLB\n");
}
-Port &
+::Port &
TableWalker::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port") {
@@ -142,6 +142,22 @@
{
}
+TableWalker::Port::Port(TableWalker *walker, System *s)
+ : MemPort(walker, s, "dma", Debug::PageTableWalker)
+{
+}
+
+void
+TableWalker::Port::walk(
+ Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, Tick delay, Request::Flags flag)
+{
+ auto state = new ReqState(cmd, addr, cacheLineSize, size,
+ data, flag, requestorId, event, delay);
+
+ sendReq(state);
+}
+
void
TableWalker::completeDrain()
{
@@ -2157,8 +2173,9 @@
}
} else {
if (isTiming) {
- port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event,
data,
-
currState->tc->getCpuPtr()->clockPeriod(),flags);
+ port->walk(MemCmd::ReadReq, descAddr, numBytes, event, data,
+ currState->tc->getCpuPtr()->clockPeriod(),flags);
+
if (queueIndex >= 0) {
DPRINTF(PageTableWalker, "Adding to walker fifo: "
"queue size before adding: %d\n",
@@ -2167,8 +2184,8 @@
currState = NULL;
}
} else if (!currState->functional) {
- port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL,
data,
- currState->tc->getCpuPtr()->clockPeriod(),
flags);
+ port->walk(MemCmd::ReadReq, descAddr, numBytes, NULL, data,
+ currState->tc->getCpuPtr()->clockPeriod(), flags);
(this->*doDescriptor)();
} else {
RequestPtr req = std::make_shared<Request>(
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 4f0373a..8865086 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2016, 2019 ARM Limited
+ * Copyright (c) 2010-2016, 2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -44,6 +44,7 @@
#include "arch/arm/regs/misc.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
+#include "base/mem_port.hh"
#include "mem/request.hh"
#include "params/ArmTableWalker.hh"
#include "sim/clocked_object.hh"
@@ -51,8 +52,6 @@
class ThreadContext;
-class DmaPort;
-
namespace ArmISA {
class Translation;
class TLB;
@@ -854,6 +853,15 @@
std::string name() const { return tableWalker->name(); }
};
+ class Port : public MemPort
+ {
+ public:
+ Port(TableWalker *walker, System *s);
+
+ void walk(Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, Tick delay, Request::Flags flag);
+ };
+
protected:
/** Queues of requests for all the different lookup levels */
@@ -867,7 +875,7 @@
Stage2MMU *stage2Mmu;
/** Port shared by the two table walkers. */
- DmaPort* port;
+ Port* port;
/** Requestor id assigned by the MMU. */
RequestorID requestorId;
@@ -937,8 +945,8 @@
DrainState drain() override;
void drainResume() override;
- Port &getPort(const std::string &if_name,
- PortID idx=InvalidPortID) override;
+ ::Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
Fault walk(const RequestPtr &req, ThreadContext *tc,
uint16_t asid, uint8_t _vmid,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bea1e16..905f41d 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1369,7 +1369,7 @@
Port *
TLB::getTableWalkerPort()
{
- return &stage2Mmu->getDMAPort();
+ return &stage2Mmu->getMemPort();
}
void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1a13779512c2862da55ef4d2dec28bf47f12eb47
Gerrit-Change-Number: 44969
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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