Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36297 )
Change subject: cpu,stats: Update stats style for base.hh and base.cc
......................................................................
cpu,stats: Update stats style for base.hh and base.cc
Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Signed-off-by: Hoa Nguyen <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36297
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/pipeline.cc
M src/cpu/minor/stats.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/trace/trace_cpu.cc
14 files changed, 64 insertions(+), 60 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index b524ad1..0c998be 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -133,6 +133,7 @@
previousCycle(0), previousState(CPU_STATE_SLEEP),
functionTraceStream(nullptr), currentFunctionStart(0),
currentFunctionEnd(0), functionEntryTick(0),
+ baseStats(this),
addressMonitor(p.numThreads),
syscallRetryLatency(p.syscallRetryLatency),
pwrGatingLatency(p.pwr_gating_latency),
@@ -368,6 +369,16 @@
ppRetiredBranches->notify(1);
}
+BaseCPU::
+BaseCPUStats::BaseCPUStats(Stats::Group *parent)
+ : Stats::Group(parent),
+ ADD_STAT(numCycles, "Number of cpu cycles simulated"),
+ ADD_STAT(numWorkItemsStarted, "Number of work items this cpu
started"),
+ ADD_STAT(numWorkItemsCompleted,
+ "Number of work items this cpu completed")
+{
+}
+
void
BaseCPU::regStats()
{
@@ -381,21 +392,6 @@
using namespace Stats;
- numCycles
- .name(name() + ".numCycles")
- .desc("number of cpu cycles simulated")
- ;
-
- numWorkItemsStarted
- .name(name() + ".numWorkItemsStarted")
- .desc("number of work items this cpu started")
- ;
-
- numWorkItemsCompleted
- .name(name() + ".numWorkItemsCompleted")
- .desc("number of work items this cpu completed")
- ;
-
int size = threadContexts.size();
if (size > 1) {
for (int i = 0; i < size; ++i) {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c793295..3d09959 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -223,8 +223,8 @@
uint32_t getPid() const { return _pid; }
void setPid(uint32_t pid) { _pid = pid; }
- inline void workItemBegin() { numWorkItemsStarted++; }
- inline void workItemEnd() { numWorkItemsCompleted++; }
+ inline void workItemBegin() { baseStats.numWorkItemsStarted++; }
+ inline void workItemEnd() { baseStats.numWorkItemsCompleted++; }
// @todo remove me after debugging with legion done
Tick instCount() { return instCnt; }
@@ -604,10 +604,14 @@
}
public:
- // Number of CPU cycles simulated
- Stats::Scalar numCycles;
- Stats::Scalar numWorkItemsStarted;
- Stats::Scalar numWorkItemsCompleted;
+ struct BaseCPUStats : public Stats::Group
+ {
+ BaseCPUStats(Stats::Group *parent);
+ // Number of CPU cycles simulated
+ Stats::Scalar numCycles;
+ Stats::Scalar numWorkItemsStarted;
+ Stats::Scalar numWorkItemsCompleted;
+ } baseStats;
private:
std::vector<AddressMonitor> addressMonitor;
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index a4a6323..70dc451 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -196,7 +196,7 @@
while (!result.empty()) {
result.pop();
}
- numCycles++;
+ baseStats.numCycles++;
Fault fault = NoFault;
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index f339ec0..cb0b4bb 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -491,7 +491,8 @@
assert(_status == Idle);
assert(!tickEvent.scheduled());
- numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
+ baseStats.numCycles +=
+ ticksToCycles(thread->lastActivate - thread->lastSuspend);
schedule(tickEvent, clockEdge(Cycles(0)));
_status = Running;
@@ -762,7 +763,7 @@
ticksExecuted = runTimer->ticksFromHostCycles(hostCyclesExecuted);
/* Update statistics */
- numCycles += simCyclesExecuted;;
+ baseStats.numCycles += simCyclesExecuted;;
stats.committedInsts += instsExecuted;
ctrInsts += instsExecuted;
system->totalNumInsts += instsExecuted;
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index d3f9157..78c2020 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -52,7 +52,7 @@
{
Pipeline::Pipeline(MinorCPU &cpu_, const MinorCPUParams ¶ms) :
- Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
+ Ticked(cpu_, &(cpu_.BaseCPU::baseStats.numCycles)),
cpu(cpu_),
allow_idling(params.enableIdling),
f1ToF2(cpu.name() + ".f1ToF2", "lines",
diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc
index b43a4a1..cf28b0f 100644
--- a/src/cpu/minor/stats.cc
+++ b/src/cpu/minor/stats.cc
@@ -59,10 +59,10 @@
quiesceCycles.prereq(quiesceCycles);
cpi.precision(6);
- cpi = base_cpu->numCycles / numInsts;
+ cpi = base_cpu->baseStats.numCycles / numInsts;
ipc.precision(6);
- ipc = numInsts / base_cpu->numCycles;
+ ipc = numInsts / base_cpu->baseStats.numCycles;
committedInstType
.init(base_cpu->numThreads, Enums::Num_OpClass)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index de14ecb..c67ee64 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -433,19 +433,19 @@
cpi
.precision(6);
- cpi = cpu->numCycles / committedInsts;
+ cpi = cpu->baseStats.numCycles / committedInsts;
totalCpi
.precision(6);
- totalCpi = cpu->numCycles / sum(committedInsts);
+ totalCpi = cpu->baseStats.numCycles / sum(committedInsts);
ipc
.precision(6);
- ipc = committedInsts / cpu->numCycles;
+ ipc = committedInsts / cpu->baseStats.numCycles;
totalIpc
.precision(6);
- totalIpc = sum(committedInsts) / cpu->numCycles;
+ totalIpc = sum(committedInsts) / cpu->baseStats.numCycles;
intRegfileReads
.prereq(intRegfileReads);
@@ -492,7 +492,7 @@
assert(!switchedOut());
assert(drainState() != DrainState::Drained);
- ++numCycles;
+ ++baseStats.numCycles;
updateCycleCounters(BaseCPU::CPU_STATE_ON);
// activity = false;
@@ -1665,7 +1665,7 @@
if (cycles > 1) {
--cycles;
cpuStats.idleCycles += cycles;
- numCycles += cycles;
+ baseStats.numCycles += cycles;
}
schedule(tickEvent, clockEdge());
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e5cf786..6f03e78 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -162,44 +162,45 @@
FetchStatGroup::FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch)
: Stats::Group(cpu, "fetch"),
ADD_STAT(icacheStallCycles,
- "Number of cycles fetch is stalled on an Icache miss"),
+ "Number of cycles fetch is stalled on an Icache miss"),
ADD_STAT(insts, "Number of instructions fetch has processed"),
ADD_STAT(branches, "Number of branches that fetch encountered"),
ADD_STAT(predictedBranches,
- "Number of branches that fetch has predicted taken"),
+ "Number of branches that fetch has predicted taken"),
ADD_STAT(cycles,
- "Number of cycles fetch has run and was not squashing or blocked"),
+ "Number of cycles fetch has run and was not squashing or "
+ "blocked"),
ADD_STAT(squashCycles, "Number of cycles fetch has spent squashing"),
ADD_STAT(tlbCycles,
- "Number of cycles fetch has spent waiting for tlb"),
+ "Number of cycles fetch has spent waiting for tlb"),
ADD_STAT(idleCycles, "Number of cycles fetch was idle"),
ADD_STAT(blockedCycles, "Number of cycles fetch has spent blocked"),
ADD_STAT(miscStallCycles,
- "Number of cycles fetch has spent waiting on interrupts,"
- "or bad addresses, or out of MSHRs"),
+ "Number of cycles fetch has spent waiting on interrupts, "
+ "or bad addresses, or out of MSHRs"),
ADD_STAT(pendingDrainCycles,
- "Number of cycles fetch has spent waiting on pipes to drain"),
+ "Number of cycles fetch has spent waiting on pipes to drain"),
ADD_STAT(noActiveThreadStallCycles,
- "Number of stall cycles due to no active thread to fetch from"),
+ "Number of stall cycles due to no active thread to fetch
from"),
ADD_STAT(pendingTrapStallCycles,
- "Number of stall cycles due to pending traps"),
+ "Number of stall cycles due to pending traps"),
ADD_STAT(pendingQuiesceStallCycles,
- "Number of stall cycles due to pending quiesce instructions"),
+ "Number of stall cycles due to pending quiesce instructions"),
ADD_STAT(icacheWaitRetryStallCycles,
- "Number of stall cycles due to full MSHR"),
+ "Number of stall cycles due to full MSHR"),
ADD_STAT(cacheLines, "Number of cache lines fetched"),
ADD_STAT(icacheSquashes,
- "Number of outstanding Icache misses that were squashed"),
+ "Number of outstanding Icache misses that were squashed"),
ADD_STAT(tlbSquashes,
- "Number of outstanding ITLB misses that were squashed"),
+ "Number of outstanding ITLB misses that were squashed"),
ADD_STAT(nisnDist,
- "Number of instructions fetched each cycle (Total)"),
+ "Number of instructions fetched each cycle (Total)"),
ADD_STAT(idleRate, "Percent of cycles fetch was idle",
- idleCycles * 100 / cpu->numCycles),
+ idleCycles * 100 / cpu->baseStats.numCycles),
ADD_STAT(branchRate, "Number of branch fetches per cycle",
- branches / cpu->numCycles),
+ branches / cpu->baseStats.numCycles),
ADD_STAT(rate, "Number of inst fetches per cycle",
- insts / cpu->numCycles)
+ insts / cpu->baseStats.numCycles)
{
icacheStallCycles
.prereq(icacheStallCycles);
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index a50a94a..9e56ed0 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -193,7 +193,7 @@
wbRate
.flags(Stats::total);
- wbRate = writebackCount / cpu->numCycles;
+ wbRate = writebackCount / cpu->baseStats.numCycles;
wbFanout
.flags(Stats::total);
@@ -213,7 +213,8 @@
ADD_STAT(numRefs, "Number of memory reference insts executed"),
ADD_STAT(numBranches, "Number of branches executed"),
ADD_STAT(numStoreInsts, "Number of stores executed"),
- ADD_STAT(numRate, "Inst execution rate", numInsts / cpu->numCycles)
+ ADD_STAT(numRate, "Inst execution rate",
+ numInsts / cpu->baseStats.numCycles)
{
numLoadInsts
.init(cpu->numThreads)
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 44af654..3538b43 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -199,7 +199,8 @@
ADD_STAT(numIssuedDist, "Number of insts issued each cycle"),
ADD_STAT(statFuBusy, "attempts to use FU when none available"),
ADD_STAT(statIssuedInstType, "Type of FU issued"),
- ADD_STAT(issueRate, "Inst issue rate", instsIssued / cpu->numCycles),
+ ADD_STAT(issueRate, "Inst issue rate",
+ instsIssued / cpu->baseStats.numCycles),
ADD_STAT(fuBusy, "FU busy when requested"),
ADD_STAT(fuBusyRate, "FU busy rate (busy events/executed inst)")
{
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 74f6cbe..c3cbd49 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -228,7 +228,7 @@
threadInfo[thread_num]->execContextStats.notIdleFraction = 1;
Cycles delta =
ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
threadInfo[thread_num]->thread->lastSuspend);
- numCycles += delta;
+ baseStats.numCycles += delta;
if (!tickEvent.scheduled()) {
//Make sure ticks are still on multiples of cycles
@@ -633,7 +633,7 @@
Tick latency = 0;
for (int i = 0; i < width || locked; ++i) {
- numCycles++;
+ baseStats.numCycles++;
updateCycleCounters(BaseCPU::CPU_STATE_ON);
if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 3d47e63..0212e70 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -157,8 +157,8 @@
}
idleFraction = Stats::constant(1.0) - notIdleFraction;
- numIdleCycles = idleFraction * cpu->numCycles;
- numBusyCycles = notIdleFraction * cpu->numCycles;
+ numIdleCycles = idleFraction * cpu->baseStats.numCycles;
+ numBusyCycles = notIdleFraction * cpu->baseStats.numCycles;
numBranches
.prereq(numBranches);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7f3c1cd..5e9eb92 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1078,7 +1078,7 @@
{
const Cycles delta(curCycle() - previousCycle);
- numCycles += delta;
+ baseStats.numCycles += delta;
previousCycle = curCycle();
}
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 57f2497..9c39e59 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -175,7 +175,7 @@
DPRINTF(TraceCPUData, "DcacheGen event.\n");
// Update stat for numCycles
- numCycles = clockEdge() / clockPeriod();
+ baseStats.numCycles = clockEdge() / clockPeriod();
dcacheGen.execute();
if (dcacheGen.isExecComplete()) {
@@ -211,7 +211,7 @@
"Number of events scheduled to trigger instruction request
generator"),
ADD_STAT(numOps, "Number of micro-ops simulated by the Trace CPU"),
ADD_STAT(cpi, "Cycles per micro-op used as a proxy for CPI",
- trace->numCycles / numOps)
+ trace->baseStats.numCycles / numOps)
{
cpi.precision(6);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36297
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Gerrit-Change-Number: 36297
Gerrit-PatchSet: 17
Gerrit-Owner: Hoa Nguyen <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Hoa Nguyen <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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