Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36297 )
Change subject: cpu,stats: Update stats style for base.hh and base.cc
......................................................................
cpu,stats: Update stats style for base.hh and base.cc
Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Signed-off-by: Hoa Nguyen <[email protected]>
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/pipeline.cc
M src/cpu/minor/stats.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/trace/trace_cpu.cc
14 files changed, 47 insertions(+), 46 deletions(-)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 8c53f8c..8d87483 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -133,6 +133,7 @@
previousCycle(0), previousState(CPU_STATE_SLEEP),
functionTraceStream(nullptr), currentFunctionStart(0),
currentFunctionEnd(0), functionEntryTick(0),
+ baseCPUStats(this),
addressMonitor(p.numThreads),
syscallRetryLatency(p.syscallRetryLatency),
pwrGatingLatency(p.pwr_gating_latency),
@@ -368,6 +369,16 @@
ppRetiredBranches->notify(1);
}
+BaseCPU::
+BaseCPUStats::BaseCPUStats(Stats::Group *parent)
+ : Stats::Group(parent),
+ ADD_STAT(numCycles, "Number of cpu cycles simulated"),
+ ADD_STAT(numWorkItemsStarted, "Number of work items this cpu
started"),
+ ADD_STAT(numWorkItemsCompleted, "Number of work items this cpu "
+ "completed")
+{
+}
+
void
BaseCPU::regStats()
{
@@ -381,21 +392,6 @@
using namespace Stats;
- numCycles
- .name(name() + ".numCycles")
- .desc("number of cpu cycles simulated")
- ;
-
- numWorkItemsStarted
- .name(name() + ".numWorkItemsStarted")
- .desc("number of work items this cpu started")
- ;
-
- numWorkItemsCompleted
- .name(name() + ".numWorkItemsCompleted")
- .desc("number of work items this cpu completed")
- ;
-
int size = threadContexts.size();
if (size > 1) {
for (int i = 0; i < size; ++i) {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index ae656ef..54726e2 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -223,8 +223,8 @@
uint32_t getPid() const { return _pid; }
void setPid(uint32_t pid) { _pid = pid; }
- inline void workItemBegin() { numWorkItemsStarted++; }
- inline void workItemEnd() { numWorkItemsCompleted++; }
+ inline void workItemBegin() { baseCPUStats.numWorkItemsStarted++; }
+ inline void workItemEnd() { baseCPUStats.numWorkItemsCompleted++; }
// @todo remove me after debugging with legion done
Tick instCount() { return instCnt; }
@@ -604,10 +604,13 @@
}
public:
- // Number of CPU cycles simulated
- Stats::Scalar numCycles;
- Stats::Scalar numWorkItemsStarted;
- Stats::Scalar numWorkItemsCompleted;
+ struct BaseCPUStats : public Stats::Group {
+ BaseCPUStats(Stats::Group *parent);
+ // Number of CPU cycles simulated
+ Stats::Scalar numCycles;
+ Stats::Scalar numWorkItemsStarted;
+ Stats::Scalar numWorkItemsCompleted;
+ } baseCPUStats;
private:
std::vector<AddressMonitor> addressMonitor;
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 4fab375..ceea661 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -196,7 +196,7 @@
while (!result.empty()) {
result.pop();
}
- numCycles++;
+ baseCPUStats.numCycles++;
Fault fault = NoFault;
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index aecd6ee..c077ead 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -492,7 +492,8 @@
assert(_status == Idle);
assert(!tickEvent.scheduled());
- numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
+ baseCPUStats.numCycles += ticksToCycles(thread->lastActivate -
+
thread->lastSuspend);
schedule(tickEvent, clockEdge(Cycles(0)));
_status = Running;
@@ -763,7 +764,7 @@
ticksExecuted = runTimer->ticksFromHostCycles(hostCyclesExecuted);
/* Update statistics */
- numCycles += simCyclesExecuted;;
+ baseCPUStats.numCycles += simCyclesExecuted;;
stats.committedInsts += instsExecuted;
ctrInsts += instsExecuted;
system->totalNumInsts += instsExecuted;
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index d3f9157..374e546 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -52,7 +52,7 @@
{
Pipeline::Pipeline(MinorCPU &cpu_, const MinorCPUParams ¶ms) :
- Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
+ Ticked(cpu_, &(cpu_.BaseCPU::baseCPUStats.numCycles)),
cpu(cpu_),
allow_idling(params.enableIdling),
f1ToF2(cpu.name() + ".f1ToF2", "lines",
diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc
index 74090c7..d2f9346 100644
--- a/src/cpu/minor/stats.cc
+++ b/src/cpu/minor/stats.cc
@@ -66,8 +66,8 @@
void MinorStats::regStats(const std::string &name, BaseCPU &baseCpu)
{
- cpi = baseCpu.numCycles / numInsts;
- ipc = numInsts / baseCpu.numCycles;
+ cpi = baseCpu.baseCPUStats.numCycles / numInsts;
+ ipc = numInsts / baseCpu.baseCPUStats.numCycles;
committedInstType
.init(baseCpu.numThreads, Enums::Num_OpClass)
.flags(Stats::total | Stats::pdf | Stats::dist);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3ce198e..732f9cc 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -492,10 +492,10 @@
.init(numThreads)
.flags(Stats::total);
- cpuStats.cpi = numCycles / cpuStats.committedInsts;
- cpuStats.totalCpi = numCycles / sum(cpuStats.committedInsts);
- cpuStats.ipc = cpuStats.committedInsts / numCycles;
- cpuStats.totalIpc = sum(cpuStats.committedInsts) / numCycles;
+ cpuStats.cpi = baseCPUStats.numCycles / cpuStats.committedInsts;
+ cpuStats.totalCpi = baseCPUStats.numCycles /
sum(cpuStats.committedInsts);
+ cpuStats.ipc = cpuStats.committedInsts / baseCPUStats.numCycles;
+ cpuStats.totalIpc = sum(cpuStats.committedInsts) /
baseCPUStats.numCycles;
this->iew.regStats();
@@ -509,7 +509,7 @@
assert(!switchedOut());
assert(drainState() != DrainState::Drained);
- ++numCycles;
+ ++baseCPUStats.numCycles;
updateCycleCounters(BaseCPU::CPU_STATE_ON);
// activity = false;
@@ -1682,7 +1682,7 @@
if (cycles > 1) {
--cycles;
cpuStats.idleCycles += cycles;
- numCycles += cycles;
+ baseCPUStats.numCycles += cycles;
}
schedule(tickEvent, clockEdge());
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d0762ca..62e2adc 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -195,11 +195,11 @@
ADD_STAT(nisnDist,
"Number of instructions fetched each cycle (Total)"),
ADD_STAT(idleRate, "Percent of cycles fetch was idle",
- idleCycles * 100 / cpu->numCycles),
+ idleCycles * 100 / cpu->baseCPUStats.numCycles),
ADD_STAT(branchRate, "Number of branch fetches per cycle",
- branches / cpu->numCycles),
+ branches / cpu->baseCPUStats.numCycles),
ADD_STAT(rate, "Number of inst fetches per cycle",
- insts / cpu->numCycles)
+ insts / cpu->baseCPUStats.numCycles)
{
icacheStallCycles
.prereq(icacheStallCycles);
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index e4cebef..d399fd4 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -177,7 +177,7 @@
ADD_STAT(executedBranches, "Number of branches executed"),
ADD_STAT(execStoreInsts, "Number of stores executed"),
ADD_STAT(execRate, "Inst execution rate",
- executedInsts / cpu->numCycles),
+ executedInsts / cpu->baseCPUStats.numCycles),
ADD_STAT(instsToCommit, "Cumulative count of insts sent to commit"),
ADD_STAT(writebackCount, "Cumulative count of insts written-back"),
ADD_STAT(producerInst, "Number of instructions producing a value"),
@@ -231,7 +231,7 @@
wbRate
.flags(total);
- wbRate = writebackCount / cpu->numCycles;
+ wbRate = writebackCount / cpu->baseCPUStats.numCycles;
wbFanout
.flags(total);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 5969254..98c0c57 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -198,7 +198,8 @@
ADD_STAT(numIssuedDist, "Number of insts issued each cycle"),
ADD_STAT(statFuBusy, "attempts to use FU when none available"),
ADD_STAT(statIssuedInstType, "Type of FU issued"),
- ADD_STAT(issueRate, "Inst issue rate", instsIssued / cpu->numCycles),
+ ADD_STAT(issueRate, "Inst issue rate",
+ instsIssued /
cpu->baseCPUStats.numCycles),
ADD_STAT(fuBusy, "FU busy when requested"),
ADD_STAT(fuBusyRate, "FU busy rate (busy events/executed inst)")
{
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 69fdc77..269a47d 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -229,7 +229,7 @@
threadInfo[thread_num]->execContextStats.notIdleFraction = 1;
Cycles delta =
ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
threadInfo[thread_num]->thread->lastSuspend);
- numCycles += delta;
+ baseCPUStats.numCycles += delta;
if (!tickEvent.scheduled()) {
//Make sure ticks are still on multiples of cycles
@@ -644,7 +644,7 @@
Tick latency = 0;
for (int i = 0; i < width || locked; ++i) {
- numCycles++;
+ baseCPUStats.numCycles++;
updateCycleCounters(BaseCPU::CPU_STATE_ON);
if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index a0af6d2..749d0b6 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -158,8 +158,8 @@
}
idleFraction = constant(1.0) - notIdleFraction;
- numIdleCycles = idleFraction * cpu->numCycles;
- numBusyCycles = notIdleFraction * cpu->numCycles;
+ numIdleCycles = idleFraction * cpu->baseCPUStats.numCycles;
+ numBusyCycles = notIdleFraction * cpu->baseCPUStats.numCycles;
numBranches
.prereq(numBranches);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 0b60506..09a44ea 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1078,7 +1078,7 @@
{
const Cycles delta(curCycle() - previousCycle);
- numCycles += delta;
+ baseCPUStats.numCycles += delta;
previousCycle = curCycle();
}
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index b2326eb..69ca5cd 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -181,7 +181,7 @@
DPRINTF(TraceCPUData, "DcacheGen event.\n");
// Update stat for numCycles
- numCycles = clockEdge() / clockPeriod();
+ baseCPUStats.numCycles = clockEdge() / clockPeriod();
dcacheGen.execute();
if (dcacheGen.isExecComplete()) {
@@ -217,7 +217,7 @@
"Number of events scheduled to trigger instruction request
generator"),
ADD_STAT(numOps, "Number of micro-ops simulated by the Trace CPU"),
ADD_STAT(cpi, "Cycles per micro-op used as a proxy for CPI",
- trace->numCycles / numOps)
+ trace->baseCPUStats.numCycles / numOps)
{
cpi.precision(6);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36297
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Gerrit-Change-Number: 36297
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen <[email protected]>
Gerrit-MessageType: newchange
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