Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34174 )
Change subject: gpu: Use X86ISA instead of TheISA in compute_unit.cc.
......................................................................
gpu: Use X86ISA instead of TheISA in compute_unit.cc.
This file is nominally not tied to the X86ISA, but in reality it is
because it reaches into the GPU TLB, which is defined unchangeably in the
X86ISA namespaces, and uses data structures within it. Rather than try to
pretend that these structures are generic, we'll instead just use X86ISA
instead of TheISA. If this really does become generic in the future, a
base class with the ISA agnostic essentials defined in it can be used
instead, and the ISA specific TLBs can defined their own derived class
which has whatever else they need. Really the compute unit shouldn't be
communicating with the TLB using sender state since those are supposed
to be little notes for the sender to keep with a transaction, not for
communicating between entities across a port.
Change-Id: Ie6573396f6c77a9a02194f5f4595eefa45d6d66b
---
M src/gpu-compute/compute_unit.cc
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index 920257d..6e24895 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1074,8 +1074,8 @@
pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index);
// This is the senderState needed by the TLB hierarchy to function
- TheISA::GpuTLB::TranslationState *translation_state =
- new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc,
false,
+ X86ISA::GpuTLB::TranslationState *translation_state =
+ new X86ISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc,
false,
pkt->senderState);
pkt->senderState = translation_state;
@@ -1167,7 +1167,7 @@
delete pkt->senderState;
// Because it's atomic operation, only need TLB translation state
- pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode,
+ pkt->senderState = new X86ISA::GpuTLB::TranslationState(TLB_mode,
shader->gpuTc);
tlbPort[tlbPort_index].sendFunctional(pkt);
@@ -1188,8 +1188,8 @@
new_pkt->req->getPaddr());
// safe_cast the senderState
- TheISA::GpuTLB::TranslationState *sender_state =
-
safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
+ X86ISA::GpuTLB::TranslationState *sender_state =
+
safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
delete sender_state->tlbEntry;
delete new_pkt;
@@ -1209,7 +1209,7 @@
new ComputeUnit::ScalarDTLBPort::SenderState(gpuDynInst);
pkt->senderState =
- new TheISA::GpuTLB::TranslationState(tlb_mode, shader->gpuTc,
false,
+ new X86ISA::GpuTLB::TranslationState(tlb_mode, shader->gpuTc,
false,
pkt->senderState);
if (scalarDTLBPort.isStalled()) {
@@ -1398,8 +1398,8 @@
computeUnit->tlbCycles += curTick();
// pop off the TLB translation state
- TheISA::GpuTLB::TranslationState *translation_state =
-
safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
+ X86ISA::GpuTLB::TranslationState *translation_state =
+
safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
// no PageFaults are permitted for data accesses
if (!translation_state->tlbEntry) {
@@ -1471,8 +1471,8 @@
DPRINTF(GPUPrefetch, "CU[%d][%d][%d][%d]: %#x was last\n",
computeUnit->cu_id, simdId, wfSlotId, mp_index, last);
- int stride = last ? (roundDown(vaddr, TheISA::PageBytes) -
- roundDown(last, TheISA::PageBytes)) >>
TheISA::PageShift
+ int stride = last ? (roundDown(vaddr, X86ISA::PageBytes) -
+ roundDown(last, X86ISA::PageBytes)) >>
X86ISA::PageShift
: 0;
DPRINTF(GPUPrefetch, "Stride is %d\n", stride);
@@ -1492,13 +1492,13 @@
// Prefetch Next few pages atomically
for (int pf = 1; pf <= computeUnit->prefetchDepth; ++pf) {
DPRINTF(GPUPrefetch, "%d * %d: %#x\n", pf, stride,
- vaddr+stride*pf*TheISA::PageBytes);
+ vaddr + stride * pf * X86ISA::PageBytes);
if (!stride)
break;
RequestPtr prefetch_req = std::make_shared<Request>(
- vaddr + stride * pf * TheISA::PageBytes,
+ vaddr + stride * pf * X86ISA::PageBytes,
sizeof(uint8_t), 0,
computeUnit->masterId(),
0, 0, nullptr);
@@ -1509,15 +1509,15 @@
// Because it's atomic operation, only need TLB translation
state
prefetch_pkt->senderState =
- new TheISA::GpuTLB::TranslationState(TLB_mode,
+ new X86ISA::GpuTLB::TranslationState(TLB_mode,
computeUnit->shader->gpuTc, true);
// Currently prefetches are zero-latency, hence the
sendFunctional
sendFunctional(prefetch_pkt);
/* safe_cast the senderState */
- TheISA::GpuTLB::TranslationState *tlb_state =
- safe_cast<TheISA::GpuTLB::TranslationState*>(
+ X86ISA::GpuTLB::TranslationState *tlb_state =
+ safe_cast<X86ISA::GpuTLB::TranslationState*>(
prefetch_pkt->senderState);
@@ -1664,8 +1664,8 @@
{
assert(pkt->senderState);
- TheISA::GpuTLB::TranslationState *translation_state =
- safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
+ X86ISA::GpuTLB::TranslationState *translation_state =
+ safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
// Page faults are not allowed
fatal_if(!translation_state->tlbEntry,
@@ -1729,8 +1729,8 @@
assert(pkt->senderState);
// pop off the TLB translation state
- TheISA::GpuTLB::TranslationState *translation_state
- = safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
+ X86ISA::GpuTLB::TranslationState *translation_state
+ = safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
bool success = translation_state->tlbEntry != nullptr;
delete translation_state->tlbEntry;
@@ -2454,7 +2454,7 @@
void
ComputeUnit::updatePageDivergenceDist(Addr addr)
{
- Addr virt_page_addr = roundDown(addr, TheISA::PageBytes);
+ Addr virt_page_addr = roundDown(addr, X86ISA::PageBytes);
if (!pagesTouched.count(virt_page_addr))
pagesTouched[virt_page_addr] = 1;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34174
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6573396f6c77a9a02194f5f4595eefa45d6d66b
Gerrit-Change-Number: 34174
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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