Hi, r, Thank you very much. You suggestion works fine. I am not quite familiar with Verilog grammar. Seems it is my fault missing the "posedge" for reset. :)
Best regards, Yujie Wen r 写道: > On Wed, Mar 11, 2009 at 11:12 AM, 温宇杰 <[email protected]> wrote: > >> always @(posedge CLK or RESET) begin >> if (RESET == 1) begin Q = 0; >> end >> > > I don't know much about iverilog but you may want to try this form: > always @(posedge CLK or posedge RESET) begin > > Regards, > -r > > > _______________________________________________ > geda-user mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
