Hi, I am writing some netlist generator in the Icarus Verilog 0.8 release for our own FPGA-like devices. But I ran into a question that whether Icarus Verilog can synthesis out flip-flops with asynchronous reset input.
When I run iverilog with command "iverilog -tfpga -parch=virtex test.v" and the content of test.v is as below: ---------------------------------------------------------------------------------- module test(D, Q, CLK, RESET); input D, CLK, RESET; output Q; reg Q; always @(posedge CLK or RESET) begin if (RESET == 1) begin Q = 0; end else begin Q = D; end end endmodule //test -------------------------------------------------------------------- iverilog will report messages like: ---------------------------------------------- test.v: 5: warning: process not synthesized. fpga target: unsynthesized behavior code. ---------------------------------------------- But if RESET is removed from the sensitivity list, synthesis works fine. Seems like iverilog cannot process asynchronous RESET signal for flip-flops. Is that true? Best regards, Yujie Wen _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
