Cheating? I did that board when pcb only supported 8 layers so yep lie steal cheat grand larceny I did what ever I could to make it fit ;) And I am still thrilled that the difference between detection on the analog channels was less then 10 pico seconds. Far below what we could directly measure on a high end lecroy scope.
Looking at the image it appears that there were as many as 8 rows deep of io from the edge. so 8 - 1 = 7 rows of inner io / 2 = 3.5 layers. for 7 rows of io 7 - 1 = 6 rows of inner io / 2 = 3 layers. So in general I agree that 7 rows of io depth can be squeezed into 3 layers, however getting to the edge of the fpga is just the start then you have to reach all the devices and the fpga itself has configuration pins scattered in such a manner as to interfere with neat orderly math. In reality there is also a relationship to board component surface area density and the number of signal layers you have to arrange traces. Fewer signal layers tends to force your components further apart. Yea about getting 6 voltage layers and 2 ground layers into the remaining 4 layers..... I do recommend rethinking only one trace between rows especially for anyone using differential IO. The real issue here separation the hobbyist from the professional is the cost of the components. Boards of this nature are likely to run into the thousands of dollars each for small quantities (pcb fabrication, components and assembly). Steve M. On Fri, 2008-03-28 at 15:08 -0400, DJ Delorie wrote: > Ok, you're cheating by using via-in pad ;-) > > I think the "generic" breakout (at least for us hobby types) is one > trace between pads, and one between vias. So you can bring out two > (signal) rows on top, two rows (through vias) to some other layer, and > one more row for each additional layer. In your example, you're > bringing out eight signal rows, so: two on top, two on next, and four > more layers for the rest, or six signal layers. > > If you can get two traces between pads, that's an extra row that can > come out on top. > > If you can get two traces between vias, it's three rows for the first > non-top layer, and two rows for each layer beyond that. For your > example, that's three on top, three on next, and one more layer for > the next two. You should have been able to do it with only three > signal layers. > > between: 1 1/2 2 > signal rows > ----------- > 1 1 1 1 > 2 1 1 1 > 3 2 1 1 > 4 2 2 2 > 5 3 2 2 > 6 4 3 2 > 7 5 4 3 > 8 6 5 3 > 9 7 6 4 > 10 8 7 4 > > None of this includes the power block at the center, or other power > pins. _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
