On Thu, 17 Jun 2021, Jakub Jelinek wrote:
> On Thu, Jun 17, 2021 at 03:21:05PM +0200, Richard Biener wrote:
> > but the difficulty is in the (const_int ..) operand to (vec_merge ..).
> > I've tried sth like
> >
> > (define_mode_attr addsub_cst [(V4DF "(const_int 5)") (V2DF "(const_int
> > 1)")
> > (V4SF "(const_int 5)") (V8SF "(const_int
> > 85)")])
>
> Have you tried making addsub_cst just "5" "1" or "85" and use (const_int
> <addsub_cst>)?
Ah, that works! Now I only have to figure out the correct attributes
and alternatives. For reference, this is what I have at the moment.
Will play further tomorrow.
(define_mode_attr addsub_cst [(V4DF "5") (V2DF "1")
(V4SF "5") (V8SF "85")])
(define_insn "vec_addsub<mode>3"
[(set (match_operand:VF_128_256 0 "register_operand" "=x")
(vec_merge:VF_128_256
(minus:VF_128_256
(match_operand:VF_128_256 1 "register_operand" "x")
(match_operand:VF_128_256 2 "nonimmediate_operand" "xm"))
(plus:VF_128_256 (match_dup 1) (match_dup 2))
(const_int <addsub_cst>)))]
"TARGET_SSE3"
"%vaddsub<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
Richard.
