Would it be possible for GCC to generate code that reserves ESI and EDI as "extended segment" registers to hold a source and destination "extended segment" of any operation.
This will be the upper 32-bits of a 64-bit address. When run on a normal 80386, such code will work fine, and ESI and EDI will always be 0, so that source and destination are always in the first 4 GiB. When run on segmentation-aware hardware, the API to obtain memory, e.g. INT 21H AH=48H (or something much better, preferably), cx will be set to 1 to indicate that a "far pointer" is being requested, and if such memory is available, EDI will be set to the segment, ie EDI = 2 will mean the 8 GiB location. The 32-bit offset will be returned via a normal register, e.g. EAX. The application will set EDI to 0 before calling the INT 21H. Only segment-aware applications will set cx to 1 in the INT 21H request. The exact same executable will thus work fine, within the 4 GiB address space, just doing unnecessary stores and loads of ESI and EDI (always 0), but on segment-aware hardware, that exact same application will have access to 16 EiB of memory, although with size_t restricted to 4 GiB (although you could break the size_t restriction by using a huge pointer instead of a far pointer). If ESI and EDI are not the most appropriate registers, something else could be chosen. Will that work? Thanks. Paul.
