On Wed, May 22, 2019 at 10:36 AM Martin Reinecke <mar...@mpa-garching.mpg.de> wrote: > > Hi Matthias! > > > I agree, we need more information from the compiler. Esp. whether the user > > specified `-mprefer-avx128` or `-mprefer-vector-width=none/128/256/512`. > > OTOH `-msve-vector-bits=N` is reported as __ARM_FEATURE_SVE_BITS. So that's > > covered. > > Almost ... except that I'd need a platform-agnostic definition. The > point is that the code does not care about the underlying hardware at > all, only for the vector length supported by it.
And then you run into AVX + SSE vs. AVX2 + SSE cases where the (optimal) length depends on the component type... I wonder if we'd want to have a 'auto' length instead ;) I suppose exposing a __BIGGEST_VECTOR__ might be possible (not for SVE though?). > > Related: PR83875 - because while we're adding things in that area, it'd be > > nice if they worked with target clones as well. > > Yes, this is a problem I've come across as well in the past. > (https://gcc.gnu.org/ml/gcc-help/2018-10/msg00118.html) > > > Are you aware of std::experimental::simd? It didn't make GCC 9.1, but you > > can easily patch your (installed) libstdc++ using > > https://github.com/VcDevel/ > > std-simd. > > This looks extremely interesting! I have to look at it in more detail, > but this might be the way to go in the future. > However, the code I'm working on may be incorporated into numpy/scipy at > some point, and the minimum required compilers for these packages are > pretty old. I can't expect more than vanilla C++11 support there. > > Cheers, > Martin >
