On Mon, May 6, 2019 at 6:02 AM Алексей Хилаев via gcc <gcc@gcc.gnu.org> wrote: > Gcc riscv won`t emit my insns, binutils and spike(riscv sim) work correctly, > but gcc don`t. I want to add min/max for integer, gcc compiling correct, sim > executing correctly. > (define_insn "*min_<X:mode><GPR:mode>" > [(set (match_operand:GPR 0 "register_operand" "=r") > (smin:GPR (match_operand:X 1 "register_operand" " r") > (match_operand:X 2 "register_operand" " r")))] > "" > "min\t%0,%1,%2" > [(set_attr "type" "move") > (set_attr "mode" "<X:MODE>")])
You must have patterns named sminXi3 where X can be s and/or d. Likewise for smaxXi3. Once the named patterns exist, then gcc will automatically call the named patterns to generate RTL when appropriate. Then later passes like combine can create new RTL from the min/max pattern RTL. See for instance how the existing FP min/max patterns work. The pattern name is important. You might also consider adding uminXi3 and umaxXi3 patterns. You can find a list of supported named patterns in the gcc docs. Also note that the RTL that you generate must look sensible. You have a smin:GPR operation that is accepting Xmode operands which is not OK. The modes must match. You can use sign_extend/zero_extend to sign/zero extend a smaller mode to a larger mode, and subreg to reduce a larger mode to a smaller one. These will have to be separate patterns. But once you have the basic smin/smax patterns, combine can create the sign_extend/whatever versions for you. See for instance how the addsi3 and addsi3_extend* patterns work. Jim
