Hi all!
One thing I miss in GCC is lack of support for the AVX512 ternary logic
instruction VPTERNLOG. This instruction evaluates any three-argument logic
function; this means that an expression like "a | b & ~c" can be folded into
single instruction; my experiments showed that up to six SIMD instructions
can be replaced this way[1]. Seems it's something worth considering.
However, instead of reporting a vague bug "it'd be nice to have..." :),
I was thinking about adding support for this instruction.
I have no experience in GCC at all, but figured out that support for this
instruction can be added with new define_insn in `gcc/config/i386/sse.md`.
My very first try was to compile just "a | b | c", so created this
rule (not really working, but is properly matched by the compiler):
(define_insn "ors_combined_into_vpternlog"
[(set
(match_operand:V8DI 0 "register_operand" "=r")
(ior:V8DI
(ior:V8DI
(match_operand:V8DI 1 "register_operand" "r")
(match_operand:V8DI 2 "register_operand" "r")
)
(match_operand:V8DI 3 "register_operand" "r")
)
)]
"TARGET_AVX512F"
"vpternlog<ssemodesuffix>\t{0xfe, %3, %2, %0%|%0%, %2, %3, 0xfe}"
[(set_attr "type" "sselog")
(set_attr "prefix" "evex")])
The main concern is if it's a proper approach? Seems that to match
other logic functions, like "a & b | c", a separate pattern is required.
Since an argument can be either negated or not, and we can use three
logic ops (or, and, xor) there would be 72 patterns. So maybe a new
optimization pass would be easier to create and maintain? (Just a silly
guess.)
I'd be grateful for any comments and advice.
best regards
Wojciech
[1] https://github.com/WojciechMula/ternary-logic
