On Wed, 1 Aug 2018 at 01:32, Bramandia Ramadhana <braman...@gmail.com> wrote: > > Hi, > > I am reading the gcc wiki page about atomic Acquire/Release memory > model: https://gcc.gnu.org/wiki/Atomic/GCCMM/AtomicSync. > > It is mentioned: > > "Both of these asserts can pass since there is no ordering imposed > between the stores in thread 1 and thread 2. > > If this example were written using the sequentially consistent model, > then one of the stores must happen-before the other (although the > order isn't determined until run-time), the values are synchronized > between threads, and if one assert passes, the other assert must > therefore fail." > > > The code snippet is as follows: > -Thread 1- > y.store (20, memory_order_release); > > -Thread 2- > x.store (10, memory_order_release); > > -Thread 3- > assert (y.load (memory_order_acquire) == 20 && x.load > (memory_order_acquire) == 0) > > -Thread 4- > assert (y.load (memory_order_acquire) == 0 && x.load > (memory_order_acquire) == 10) > > In my limited understanding of the C++ memory model, it is possible > the 2 asserts can pass even in sequentially consistent model. > > Consider the following interleaving: > - First check of thread 4 runs, it passes since y is 0 > - Thread 1 runs, y is now 20 > - Thread 3 runs, the assert passed since y = 20 and x = 0 > - Thread 2 runs, x is now 10 > - The second check of thread 4 runs, it also passes since x is now 10. > Hence, the assert passed. > > Am I missing something? Can someone shed a light?
>From a quick read, I think you're right. The wiki example seems to assume that both branches of the && conditions in the assertions happen atomically.
