Vitalijus Jefišovas kirjoitti 16.11.2017 klo 18:54:
On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
other registers onto the psp stack, and then jumps to interrupt routine,
when it finishes, NVIC restores these registers, and jumps back to user’s
function.
What is happening under the hood, NVIC only stacks 4 registers, r0, r1, r2,
r3. The other ones r4-r12 is developer’s responsibility.
I was looking at assembly code generated by GCC and there are plenty of
instructions using r4-r12 registers.
How does GCC handle scenario when execution is switched to unknown
procedure, which changes all of these registers?
Cortex-M is an ARM-architecture processor or how? So one uses things
related to ARM
or how?
With ARM one uses function attributes available for ARM when the
question is about a
special function like an ISR ("Interrupt Service Routine"). From the
GCC 7.2.0 manual :
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6.31.4 ARM Function Attributes
These function attributes are supported for ARM targets:
interrupt
Use this attribute to indicate that the specified function is an
interrupt handler.
The compiler generates function entry and exit sequences suitable for
use in an
interrupt handler when this attribute is present.
You can specify the kind of interrupt to be handled by adding an optional
parameter to the interrupt attribute like this:
void f () __attribute__ ((interrupt ("IRQ")));
Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and
UNDEF.
On ARMv7-M the interrupt type is ignored, and the attribute means the
function
may be called with a word-aligned stack pointer.
isr
Use this attribute on ARM to write Interrupt Service Routines. This
is an alias
to the interrupt attribute above.
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How this attribute works with the NVIC I don't know but using the aimed
attribute
and seeing the result is one way to see what will happen...
