Hi all,
we are currently porting GCC to our own RISC architecture, which is
similar to MIPS. This architecture contains one unconditional branch
delay slot. The effect I noticed also occurs on MIPS, so I will be
focusing on that architecture in the following.
I noticed that GCC never puts accesses to volatile variables into the
branch delay slot. For example, compiling this code on MIPS:
extern volatile int a;
void writeA() {
a = 42;
}
Leads to this assembly code:
writeA:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
lui $28,%hi(__gnu_local_gp)
addiu $28,$28,%lo(__gnu_local_gp)
lw $2,%got(a)($28)
li $3,42 # 0x2a
sw $3,0($2)
jr $31
nop
jr's delay slot is not filled. However, if the declaration of a is
changed to `extern int a`, the delay slot is filled with the sw.
The function responsible for this behavior seems to be
resource_conflicts_p in reorg.c. Sadly, I could not find any comments
explaining why volatile accesses cannot be put into delay slots.
What is the reason for this behavior? I am unable to think of any
situation where allowing volatile memory accesses in branch delay slots
leads to problems. Am I missing a case? Or are negative effects limited
to other architectures?
Regards,
Jakob
--
M.Sc. Jakob Wenzel
Fachgebiet Rechnersysteme
Fachbereich 18, Elektrotechnik und Informationstechnik
Technische Universität Darmstadt
Merckstraße 25
D-64283 Darmstadt
Tel: 06151-1621154
