[Abe wrote:]
[snip]
Even without cmove to/from main memory, two cmoves back-to-back with opposite
conditions could still be used, e.g. [not for a real-world ISA]:
load X[x] -> reg1
load Y[y] -> reg2
cmove c ? reg1 -> reg3
cmove (!c) ? reg2 -> reg3
Or even better if the ISA can support something like:
load X[x] -> reg1
load Y[y] -> reg2
cmove (c ? reg1 : reg2) -> reg3
However, this is a code-gen issue from my POV, and at the present time all the
if-conversion work is occurring at the GIMPLE level.
If anybody reading this knows how I could make the if converter generate GIMPLE
that leads to code-gen that is better for at
least one ISA
[Alan wrote:]
Ramana writes that your patch for PR46029 generates more 'csel's (i.e. the
second form you write)
for AArch64: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01721.html
Thanks to Ramana for doing that analysis and thanks to Alan for informing me.
of course this says nothing about whether there is *some* other ISA that gets
regressed!
After finishing fixing the known regressions, I intend/plan to reg-test for
AArch64;
after that, I think I`m going to need some community help to reg-test for other
ISAs.
Regards,
Abe
