> Does this happen systematically with the compare insn or is it isolated?

I encountered this problem only once in gcc testsuite 
(gcc.c-torture/execute/builtins/strncat-chk.c).
I think the problem is quite rare because gcc does not put often a parallel 
compare insn into the delay slot of a conditional jump, 
and when it happens it's not certain that the register clobbered by the 
parallel compare is used in the fall-through path after the conditional jump.
So I would say the problem is isolated.

> This looks like a bug in the dbr pass (several of them have been fixed since
> 4.5.2) but it's impossible to be more precise without further details.  The 
> support of annulled instructions is not required for proper operation.

My current investigation showed that when I comment the call to 
'fill_eager_delay_slots' in ' reorg.c:dbr_schedule' the problem disappear. 
The problem does not come from the 2 others techniques for filling delay slots 
: 'fill_simple_delay_slots' or 'relax_delay_slots'.

To illustrate the problem previously described in asm, I copied and commented 
the rtl dumps below :

--------------------------------------------------------------------------
* Dumps before dbr scheduling (dump xx.214r.barriers) 
--------------------------------------------------------------------------

### compare $R5 to 0 ($R1 is clobbered)
(insn 38 97 39 test.c:14:21 (parallel [
            (set:CC (reg:CC 56 $CCI)
                (compare:CC (reg:SI 18 $R5 [108])
                    (const_int 0 [0x0])))
            (clobber (reg:SI 18 $R1 [109]))
        ]) 45 {compare} (expr_list:REG_DEAD (reg:SI 18 $R5 [108])
        (nil)))

### conditionnal branch to label 51
(jump_insn 39 38 71 test.c:14:21 (set (pc)
        (if_then_else (eq (reg:CC 56 $CCI)
                (const_int 0 [0x0]))
            (label_ref 51)
            (pc))) 131 {jmpif} (expr_list:REG_DEAD (reg:CC 56 $CCI)
        (expr_list:REG_BR_PROB (const_int 900 [0x384])
            (nil)))
 -> 51)

(code_label 71 39 70 6 "" [1 uses])

(note 70 71 41 [bb 3] NOTE_INSN_BASIC_BLOCK)

### increment $R0 in fall-through path
(insn 41 70 43 test.c:16:7 (set (reg/v:SI 16 $R0 [orig:85 len ] [85])
        (plus:SI (reg/v:SI 16 $R0 [orig:85 len ] [85])
            (const_int 1 [0x1]))) 40 {addsi3_nocompare} (nil))

### I have hidden some insn not very usefull
[...]

### target of the conditionnal jump
(code_label 51 50 52 3 "" [1 uses])

(note 52 51 53 [bb 4] NOTE_INSN_BASIC_BLOCK)

### compare $R4 to $R0 ($R0 is clobbered)
(insn 53 52 56 test.c:19:11 (parallel [
            (set:CC (reg:CC 56 $CCI)
                (compare:CC (reg/v:SI 20 $R4 [orig:93 size ] [93])
                    (reg/v:SI 16 $R0 [orig:85 len ] [85])))
            (clobber (reg:SI 16 $R0 [117]))
        ]) 45 {compare} (expr_list:REG_DEAD (reg/v:SI 20 $R4 [orig:93 size ] 
[93])
        (expr_list:REG_DEAD (reg/v:SI 16 $R0 [orig:85 len ] [85])
            (nil))))

(note 56 53 57 NOTE_INSN_DELETED)

### conditionnal call symbol_ref
(call_insn 57 56 60 test.c:20:16 (cond_exec (leu (reg:CC 56 $CCI)
            (const_int 0 [0x0]))
        (parallel [
                (set (reg:SI 16 $R0)
                    (call (mem:SI (symbol_ref:SI ("__chk_fail") [flags 0x41]  
<function_decl 0x2b690a9f8d00 __chk_fail>) [0 S4 A32])
                        (const_int 0 [0x0])))
                (clobber (reg:SI 1 $C1))
            ])) 161 {call_value_cond} (expr_list:REG_DEAD (reg:SI 1 $C1)



--------------------------------------------------------------------------
* Dumps after dbr scheduling (dump xx.c.215r.db)
--------------------------------------------------------------------------

### compare $R5 to 0 ($R1 is clobbered)
(insn 38 97 121 test.c:14:21 (parallel [
            (set:CC (reg:CC 56 $CCI)
                (compare:CC (reg:SI 18 $R5 [108])
                    (const_int 0 [0x0])))
            (clobber (reg:SI 18 $R1 [109]))
        ]) 45 {compare} (expr_list:REG_DEAD (reg:SI 18 $R5 [108])
        (nil)))

### conditionnal branch to label 51 with delay slot filled by parallel [compare 
$R4 to $R0, clobber $R0].
### the parallel compare was taken from the conditional jump 'target' path and 
should not have any side effect
### on the 'fall-through' path. But unfortunately the clobber $R0 has side 
effect ...
(insn 121 38 70 test.c:14:21 (sequence [
            (jump_insn 39 38 119 test.c:14:21 (set (pc)
                    (if_then_else (eq (reg:CC 56 $CCI)
                            (const_int 0 [0x0]))
                        (label_ref:SI 120)
                        (pc))) 131 {jmpif} (expr_list:REG_BR_PRED (const_int 48 
[0x30])
                    (expr_list:REG_DEAD (reg:CC 56 $CCI)
                        (expr_list:REG_BR_PROB (const_int 900 [0x384])
                            (nil))))
             -> 120)
            (insn/s 119 39 70 (parallel [
                        (set:CC (reg:CC 56 $CCI)
                            (compare:CC (reg/v:SI 20 $R4 [orig:93 size ] [93])
                                (reg/v:SI 16 $R0 [orig:85 len ] [85])))
                        (clobber (reg:SI 16 $R0 [117]))
                    ]) 45 {compare} (nil))
        ]) -1 (nil))
        
(note 70 121 41 [bb 3] NOTE_INSN_BASIC_BLOCK)

### increment $R0 in fall-through path, ,   but $R0 was modified by parallel 
[compare $R4 to $R0, clobber $R0]       
(insn 41 70 43 test.c:16:7 (set (reg/v:SI 16 $R0 [orig:85 len ] [85])
        (plus:SI (reg/v:SI 16 $R0 [orig:85 len ] [85])
            (const_int 1 [0x1]))) 40 {addsi3_nocompare} (nil))

### I have hidden some insn not very usefull
[...]

### target of the conditionnal jump
(code_label 120 56 57 9 "" [1 uses])

### conditionnal call symbol_ref
(call_insn 57 120 60 test.c:20:16 (cond_exec (leu (reg:CC 56 $CCI)
            (const_int 0 [0x0]))
        (parallel [
                (set (reg:SI 16 $R0)
                    (call (mem:SI (symbol_ref:SI ("__chk_fail") [flags 0x41]  
<function_decl 0x2b690a9f8d00 __chk_fail>) [0 S4 A32])
                        (const_int 0 [0x0])))
                (clobber (reg:SI 1 $C1))
            ])) 161 {call_value_cond} (expr_list:REG_DEAD (reg:SI 1 $C1)



Regards,

   Selim Belbachir


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