On Fri, Jul 19, 2013 at 04:22:48PM -0700, Carrot Wei wrote: > On Wed, Jul 17, 2013 at 6:01 PM, David Edelsohn <[email protected]> wrote: > > On Wed, Jul 17, 2013 at 7:27 PM, Carrot Wei <[email protected]> wrote: > >> Hi > >> > >> When I tried to build 444.namd with options "-O2 -m64 -mvsx > >> -mcpu=power7", I can see vsx instructions are actually used, there are > >> many xs- started instructions, but none of them use high registers > >> [vsr32 -vsr63], does anybody know the reason? > >> > >> One example is function calc_pair_energy_fullelect in file > >> ComputeNonbondedUtil.o, there are many vsr register spilling but high > >> vsr registers are never used. > > > > For scalar floating point, not vector floating point, GCC currently > > uses only the lower VSRs because the upper registers only allow > > indexed addressing modes (register + register) and not displacement > > forms. It's one register class with different valid addressing forms > > depending on the register number, which is difficult for GCC. We did > > not want to disable displacement address form in the initial support. > > In insn patterns the register class is usually not directly used, instead > different predicates and constraints are used. So can we use different > predicates and constraints in memory access instructions and floating > point arithmetic instructions?
Unfortunately, move patterns are special. At the point of register allocation, you need to have only one pattern that does a move of a given type. Predicates can only work on a single operand, so a a predicate operating on a memory operand has no idea what register is being loaded or stored. Constraints will allow you to select the different patterns, and those are used. Then in the secondary reload stage, you are given the move and have various ways to 'fix' it. Adding those fixes to the secondary reload hooks is way to deal with machines that have different address formats for different registers. Unfortunately the first machines GCC originally targeted (68k, vax) had general addressing formats that worked everywhere, and later machines you knew for a given type what type of addressing could be used. In the PowerPC you don't want register+offset if you are targetting VSX registers, while you don't want register+register if you loading the value into a GPR register and it is larger than a single register. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: [email protected], phone: +1 (978) 899-4797
