On Tue, 2012-09-11 at 20:20 -0600, Jeff Law wrote: > > These requirements seem to conflict. Am I right about this or are the > > comments wrong or am I confused? I think this problem is the basis of > > bug 54128, a bootstrap failure on MIPS, though the problem seems generic > > to any system with delay slots. > I haven't looked at 54128, but yes, I think you're generally right about > the conflict. Not sure what the implications are in terms of the > failure mode -- it would seem to me that we wouldn't get good debug > info. However, I'm not sure offhand how it'd cause a bootstrap error. > > jeff
The bootstrap error is caused by a stage2/stage3 comparison failure. Because the delay slot pass moved some instructions (but not their associated debug instructions) we no longer generate the same code with and without debug info. The change in code is due to a change in register allocation which is coming from build_insn_chain where it looks at all the instructions (debug and regular) to figure out register availability. My original fix for the bootstrap problem was to not have build_insn_chain look at debug instructions but Jakub Jelinek thought that that was not fixing the real bug but compensating for another problem. He was right and that other problem is the variable tracking / delay slot conflict. Steve Ellcey sell...@mips.com
