I'm running into issues with the MSP430 and use of PSImode in packed structures. Here the native word size is HImode, but all general purpose registers are capable of holding and operating on PSImode (=20 bit) values.
Due to instruction set limitations, on this architecture: (subreg:HI (reg:PSI 0)) is fine, but (subreg:HI (reg:PSI 2)) is inexpressible. The upper 4 bits can only be accessed with multiple shift instructions. CANNOT_CHANGE_MODE_CLASS doesn't provide the control to express this restriction on subregs. The only way I've found to tell gcc this is to hack validate_subreg to rule out non-zero offsets on PSImode. Is there a non-hack way to tell GCC about this limitation? More generally, is there a way to tell GCC not to try to decompose SImode operations into subregs even though word_mode is HImode? I've got HARD_REGNO_NREGS, HARD_REGNO_NREGS_HAS_PADDING, and REGMODE_NATURAL_SIZE set up as accurately as I can: #define MSP430_MODE_NREGS(MODE) \ (PSImode == (MODE) \ ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) #define HARD_REGNO_NREGS(REGNO, MODE) MSP430_MODE_NREGS(MODE) #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 #define MODES_TIEABLE_P(MODE1, MODE2) \ ((PSImode != (MODE1) || PSImode == (MODE2)) \ && (PSImode != (MODE2) || 1 == MSP430_MODE_NREGS (MODE1))) #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) (PSImode == (MODE)) #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) (PSImode == (MODE) ? 2 : MSP430_MODE_NREGS(MODE)) #define REGMODE_NATURAL_SIZE(MODE) (PSImode == (MODE) ? 2*UNITS_PER_WORD : UNITS_PER_WORD) Thanks. Peter
