Hi,
I've committed the following patch.
It should even perform better since we are able to often get rid of the
instructions extracting the condition code into a register (ipm, srl).
If all targets have been migrated the files probably could be merged?!
Bye,
-Andreas-
2012-06-15 Andreas Krebbel <andreas.kreb...@de.ibm.com>
* sysdep/s390/locks.h (compare_and_swap, release_set)
(read_barrier, write_barrier): Use the GCC atomic builtins.
---
libjava/sysdep/s390/locks.h | 24 !!!!!!!!!!!!!!!!!!!!!!!!
1 file changed, 24 modifications(!)
Index: libjava/sysdep/s390/locks.h
===================================================================
*** libjava/sysdep/s390/locks.h.orig
--- libjava/sysdep/s390/locks.h
***************
*** 1,6 ****
// locks.h - Thread synchronization primitives. S/390 implementation.
! /* Copyright (C) 2002 Free Software Foundation
This file is part of libgcj.
--- 1,6 ----
// locks.h - Thread synchronization primitives. S/390 implementation.
! /* Copyright (C) 2002-2012 Free Software Foundation
This file is part of libgcj.
*************** inline static bool
*** 22,42 ****
compare_and_swap(volatile obj_addr_t *addr,
obj_addr_t old, obj_addr_t new_val)
{
! int result;
!
! __asm__ __volatile__ (
! #ifndef __s390x__
! " cs %1,%2,0(%3)\n"
! #else
! " csg %1,%2,0(%3)\n"
! #endif
! " ipm %0\n"
! " srl %0,28\n"
! : "=&d" (result), "+d" (old)
! : "d" (new_val), "a" (addr)
! : "cc", "memory");
!
! return result == 0;
}
// Set *addr to new_val with release semantics, i.e. making sure
--- 22,28 ----
compare_and_swap(volatile obj_addr_t *addr,
obj_addr_t old, obj_addr_t new_val)
{
! return __sync_bool_compare_and_swap (addr, old, new_val);
}
// Set *addr to new_val with release semantics, i.e. making sure
*************** compare_and_swap(volatile obj_addr_t *ad
*** 45,51 ****
inline static void
release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
{
! __asm__ __volatile__("bcr 15,0" : : : "memory");
*(addr) = new_val;
}
--- 31,37 ----
inline static void
release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
{
! __sync_synchronize ();
*(addr) = new_val;
}
*************** compare_and_swap_release(volatile obj_ad
*** 64,70 ****
inline static void
read_barrier()
{
! __asm__ __volatile__("bcr 15,0" : : : "memory");
}
// Ensure that prior stores to memory are completed with respect to other
--- 50,56 ----
inline static void
read_barrier()
{
! __sync_synchronize ();
}
// Ensure that prior stores to memory are completed with respect to other
*************** read_barrier()
*** 72,77 ****
inline static void
write_barrier()
{
! __asm__ __volatile__("bcr 15,0" : : : "memory");
}
#endif
--- 58,63 ----
inline static void
write_barrier()
{
! __sync_synchronize ();
}
#endif
