On 04/27/2012 11:31 PM, Greg McGary wrote:
I'm working on a port that does loads& stores in two phases. Every load/store is funneled through the intermediate registers "ld" and "st" standing between memory and the rest of the register file.Example: ld=4(rB) ... ... rC=ld st=rD 8(rB)=st rB is a base address register, rC and rD are data regs. The ... represents load delay cycles. The CPU has only a single instance of "ld", but the machine description defines five in order to allow overlapping live ranges to pipeline loads. My mov insn patterns have constraints so that a memory destination pairs with the "st" register source, and a memory source pairs with "ld" destination reg. The trouble is that register allocation doesn't understand the constraint, so it loads/stores from/to random data registers.
You may wish to look at the C6X port, which also has load delay slots.
Is there a way to confine register allocation to the "ld" and "st" classes, or is it better to let IRA do what it wants, then fixup after reload with splits to turn single insn rC=MEM into the insn pair ld=MEM ... rC=ld ?
Don't expose the detail to IRA. Split the loads before the final scheduling pass and use the delay_pair mechanism to ensure things are scheduled correctly.
Bernd
