Feng LI <nemoking...@gmail.com> writes: > Thanks, it helps a lot! One more question is that during split phase, > I'll generate 2 instructions in the following order for some reason, > CLC; > CMOVC reg imm32; > > But I need to keep the following condition: > 1. The compiler will not optimize out the code or break the sequence > here. I'm doing the split phase after "reload_completed". > 2. Store the REG CC before CLC, and restore after CMOVC. > > Is there some way to do that?
You can write any instruction string you like manually, including two or four instructions. Offhand I don't know of any way to get the compiler to save CC for you around your instruction. That's a stiff requirement. Ian > On Mon, Nov 14, 2011 at 7:59 AM, Ian Lance Taylor <i...@google.com> wrote: >> Feng LI <nemoking...@gmail.com> writes: >> >>> I'm working on a gcc backend, we need to use the information of the >>> allocated hardware register to generate the code from builtin >>> functions. But at the context in ix86_expand_builtin, where I could >>> get the operands which the registers are pseudo registers >>> (REGNO(op)>FIRST_PSEUDO_REGISTER). >>> >>> Do you know where could I get the information of the hardware register >>> and generate assemble code from there? >> >> At the point where ix86_expand_builtin is called, the hardware register >> is not known. >> >> Typically this kind of thing would be handled via a >> define_insn_and_split which represents the operation in some general way >> (probably using an UNSPEC) before reload and then splits after reload >> based on the registers it winds up seeing. >> >> Ian >>
