On 05/26/2011 06:53 AM, Georg-Johann Lay wrote:
> Trying to track faulty code generation because of a missing input
> reload, I got lost in reload and need some help.
>
> The insn to reload (insn 7) is
>
> (set (subreg:QI (reg:HI 28) 0)
> (const_int 0))
>
> This insn generates one output reload (.ira dump)
>
> Reloads for insn # 7
> Reload 0: reload_out (HI) = (reg/v:HI 28 r28 [orig:43 y ] [43])
> GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
> reload_out_reg: (reg/v:HI 28 r28 [orig:43 y ] [43])
> reload_reg_rtx: (reg:HI 24 r24)
>
> which eventually generates code
>
> (insn 7 6 17 2 (set (reg:QI 24 r24)
> (const_int 0 [0])) pr46779-1.c:34 4 {*movqi}
> (nil))
>
> (insn 17 7 8 2 (set (reg/v:HI 28 r28 [orig:43 y ] [43])
> (reg:HI 24 r24)) pr46779-1.c:34 10 {*movhi}
> (nil))
>
> so there is a missing input reload...
Don't see a strict-low-part here. Why do you believe that this
should have an input reload?
> i.e. prior to insn 7 there must be
> something like
>
> (set (reg:HI 28)
> (reg:HI 24))
Why do you believe that? It looks to me that we've done exactly
as requested, namely, set the low BITS_PER_UNIT of r28 to zero
while leaving the high BITS_PER_UNIT of r28 undefined.
Perhaps the original subreg shouldn't have been there?
r~
