On 2/16/2011 3:46 PM, H.J. Lu wrote: > On Wed, Feb 16, 2011 at 12:39 PM, Andrew Pinski <pins...@gmail.com> wrote: >> On Wed, Feb 16, 2011 at 12:35 PM, Chris Metcalf <cmetc...@tilera.com> wrote: >>> For what it's worth, the Tilera 64-bit architecture (forthcoming) includes >>> support for a 32-bit compatibility layer that is similar to x32. It uses >>> 64-bit registers throughout (e.g. for double and long long), but 32-bit >>> addresses. The addresses between 2GB and 4GB are not directly usable as >>> 64-bit addresses since we sign-extend all 32-bit values to make the ISA >>> more straightforward. We use the "compat" layer to provide our syscall >>> table, since we don't have a traditional compatibility layer in this mode >>> (unlike x86_64 and i386). >> This sounds more like MIPS' n32 than x32 really. >> > Yes, x32 can access the full 4GB address space. There are some > additional optimizations which can be done in x32, but not in x86-64 > small model.
Just to be clear, the "-m32" mode in our 64-bit architecture can access the full 4GB address space, but since "-m32" pointers are sign-extended in the high 32 bits, the kernel/userspace boundary has to convert between a sign-extended userspace pointer and a regular zero-extended pointer that the kernel wants to see. -- Chris Metcalf, Tilera Corp. http://www.tilera.com
