>> * CONFIG_IU_MUL_LATENCY_2: Implementation options for the integer multiplier. >> Type Implementation issue-rate/latency >> 2-clocks 32x32 pipelined multiplier 1/2 >> 4-clocks 16x16 standard multiplier 4/4 >> 5-clocks 16x16 pipelined multiplier 4/5
I'm not shure how I should model this in gcc. I'm not that familiar with the gcc internals. Maybe someone could assist me? >> GR FPU: 1/4, with FDIV? 16 and FSQRT? 24 cycles, >> non-pipelined on separate unit >> GR FPU Lite: 8/8, with FDIVS/FDIVD/FSQRTS/FSQRTD 31/57/46/57 cycles, >> non-pipelined on same unit I could add a tune option that would switch the processor cost struct for FPU/FPU-lite. -- Greetings Konrad
