On 10/29/2010 06:18 PM, Georg Lay wrote:
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (match_operand:SI 3 "register_operand" ""))]
"..."
[(set (match_dup 3)
(and:SI (match_dup 1)
(match_dup 4)))
(set (match_dup 0)
(xor:SI (match_dup 3)
(match_dup 1)))]
Again, it's not really my field but I think this should be written as
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (match_scratch:SI 3 ""))]
""
[(set (match_dup 3)
(and:SI (match_dup 1)
(match_dup 4)))
(set (match_dup 0)
(xor:SI (match_dup 3)
(match_dup 1)))]
and the define_insn should also use match_scratch. I'm looking at
config/i386/i386.md, pattern fix_trunc<mode>_i387_fisttp_with_temp and
the two following splits.
If you do it pre-reload, register allocation should not have any problem
allocating operands 0 and 3 to the same register. It sounds to me like
you're doing your own register allocation using peepholes. :)
Paolo
