Paolo Bonzini schrieb:
> On 10/29/2010 05:08 PM, Georg Lay wrote:
>> As far as I understand the internals, peephole2 matches due to
>> predicates and
>> condition, it does not care for constraints (except for optional
>> match_scratch)
> 
> Yes, I was referring as "using constraints in the define_insn".  But
> you're dong that as far as I see.
> 
>> Maybe it's better to write it as a split1 that works prior to
>> reload instead of split2 that works after reload.
> 
> Yes, a split1 sounds much better.  It will give much more freedom to
> reload and the register allocation to do exactly the liveness-based kind
> of optimization that you're doing with a peephole.

Ok, if I use the following the split is still after reload...

(define_insn_and_split ""
  [(set (match_operand:SI 0 "register_operand"          "=d")
        (and:SI (match_operand:SI 1 "register_operand"   "d")
                (match_operand:SI 2 "const_int_operand"  "n")))
   (clobber (match_scratch:SI 3                         "=&d"))]
  "..."
  "#"
  "&& reload_completed"
  [(set (match_dup 3)
        (and:SI (match_dup 1)
                (match_dup 4)))
   (set (match_dup 0)
        (xor:SI (match_dup 3)
                (match_dup 1)))]
  ...)

And I do not know if it is wise to increase register pressure witch might lead
to more spills. And if I try the pre-reload split

(define_split
  [(set (match_operand:SI 0 "register_operand"           "")
        (and:SI (match_operand:SI 1 "register_operand"   "")
                (match_operand:SI 2 "const_int_operand"  "")))
   (clobber (match_operand:SI 3 "register_operand" ""))]
  "..."
  [(set (match_dup 3)
        (and:SI (match_dup 1)
                (match_dup 4)))
   (set (match_dup 0)
        (xor:SI (match_dup 3)
                (match_dup 1)))]

the split does not occur and I get worse code.

In fact there is no way to do pre-reload RTL-algebra in the BE. Even this simple
case fails (I guess because there is no spare reg in the respective pass,
combine or split1). The internals are not very helpful when you try to learn how
RTL-transforms are best made in the BE. Would help much if gen_reg_rtx was
allowed in these situations.

If I use expand then combine won't see an AND and so I have no more the
possibility to guide the combiner in the direction of complex patterns.

Georg




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