I have a single issue pipeline that I need to schedule more accurately. For the most part this is fine but the CPU is a 32-bit design but for 64-bit opcodes (DImode or DFmode) I need to generate 2 opcodes and not one, but these only appear as a single instruction until after reload has run. When the sched1 pass runs it causes unecessary code motion that is pessimizing things because it sees these 2 instruction sequences as being able to be issued on each new cycle. After reload these instructions get split to their 32-bit constituents but by then it's too late to undo much of what sched1 already did.
Has anyone else already solved this problem? A quick look through lots of backends didn't give me any obvious examples. If not then does anyone have any advice on which of the target hooks (if any will be appropriate) might help me. Thanks, Dave
