Joern Rennecke <joern.renne...@embecosm.com> wrote:
> I've found two bugs in truncdfsf2;
> I've also added back a number of hunks that Naveen had dropped.
>
> Note that most of the patch has been prepared in 2006, so that is the
> proper most recent copyright date for those files that haven't been touched
> save for swapping the Copyright notice.
I've got some regressions with "make check" on sh4-unknown-linux-gnu.
It looks that all of them are failed with the undefined references to
__unorddf2/__unordsf2 when -mieee enabled.
I'm trying the attached patch over sh-softfp-20100718-2131 patch.
All regressions go away with it on cross sh4-unknown-linux-gnu,
though the native bootstrap will take a few days more.
BTW, it looks that softfp __unord?f2 routines check signaling NaNs
only. This makes __builtin_isnan return false for quiet NaNs for
which current fp-bit ones return true when -mieee enabled. Perhaps
that change of behavior might be OK for software FP.
Regards,
kaz
--
diff -uprN ORIG/trunk/gcc/config/sh/ieee-754-df.S
trunk/gcc/config/sh/ieee-754-df.S
--- ORIG/trunk/gcc/config/sh/ieee-754-df.S 2010-07-20 11:39:29.000000000
+0900
+++ trunk/gcc/config/sh/ieee-754-df.S 2010-07-20 11:36:15.000000000 +0900
@@ -23,11 +23,11 @@ see the files COPYING3 and COPYING.RUNTI
!! STMicroelectronics ST40 CPUs
!! Contributed by J"orn Rennecke joern.renne...@st.com
-#ifndef __SH_FPU_DOUBLE__
-
#include "lib1funcs.h"
#include "insn-constants.h"
+#ifndef __SH_FPU_DOUBLE__
+
/* Double-precision floating-point emulation.
We handle NANs, +-infinity, and +-zero.
However, we assume that for NANs, the topmost bit of the fraction is set.
*/
@@ -123,7 +123,7 @@ GLOBAL(unorddf2):
mov.l LOCAL(c_DF_NAN_MASK),r1
not DBL0H,r0
tst r1,r0
- not r6,r0
+ not DBL1H,r0
bt LOCAL(unord)
tst r1,r0
LOCAL(unord):
@@ -788,4 +788,52 @@ LOCAL(x7ff80000):
#endif /* L_divdf3 */
#endif /* DYN_SHIFT */
+#else /* __SH_FPU_DOUBLE__ */
+
+#ifdef L_unorddf2
+ .balign 4
+ .global GLOBAL(unorddf2)
+ FUNC(GLOBAL(unorddf2))
+GLOBAL(unorddf2):
+ flds fr4,fpul
+ sts fpul,r4
+ shll r4
+ mov.l LOCAL(c_DF_QNAN_MASK),r1
+ shlr r4
+ cmp/eq r4,r1
+ bf/s LOCAL(unord_check_qnan0)
+ flds fr5,fpul
+ sts fpul,r5
+ tst r5,r5
+ bt LOCAL(unord_next)
+LOCAL(unord_check_qnan0):
+ not r4,r0
+ tst r1,r0
+ bt LOCAL(unord)
+LOCAL(unord_next):
+ flds fr6,fpul
+ sts fpul,r6
+ shll r6
+ shlr r6
+ cmp/eq r6,r1
+ bf/s LOCAL(unord_check_qnan1)
+ flds fr7,fpul
+ sts fpul,r7
+ tst r7,r7
+ bt LOCAL(unord_fail)
+LOCAL(unord_check_qnan1):
+ not r6,r0
+ tst r1,r0
+LOCAL(unord):
+ rts
+ movt r0
+LOCAL(unord_fail):
+ rts
+ mov #0,r0
+ .balign 4
+LOCAL(c_DF_QNAN_MASK):
+ .long 0x7ff00000
+ ENDFUNC(GLOBAL(unorddf2))
+#endif /* L_unorddf2 */
+
#endif /* __SH_FPU_DOUBLE__ */
diff -uprN ORIG/trunk/gcc/config/sh/ieee-754-sf.S
trunk/gcc/config/sh/ieee-754-sf.S
--- ORIG/trunk/gcc/config/sh/ieee-754-sf.S 2010-07-20 11:39:30.000000000
+0900
+++ trunk/gcc/config/sh/ieee-754-sf.S 2010-07-20 11:35:58.000000000 +0900
@@ -23,11 +23,11 @@ see the files COPYING3 and COPYING.RUNTI
!! STMicroelectronics ST40 CPUs
!! Contributed by J"orn Rennecke joern.renne...@st.com
-#ifndef __SH_FPU_ANY__
-
#include "lib1funcs.h"
#include "insn-constants.h"
+#ifndef __SH_FPU_ANY__
+
/* Single-precision floating-point emulation.
We handle NANs, +-infinity, and +-zero.
However, we assume that for NANs, the topmost bit of the fraction is set.
*/
@@ -689,4 +689,42 @@ LOCAL(tab):
#endif /* L_hypotf */
#endif /* DYN_SHIFT */
+#else /* __SH_FPU_ANY__ */
+
+#ifdef L_unordsf2
+ .balign 4
+ .global GLOBAL(unordsf2)
+ FUNC(GLOBAL(unordsf2))
+GLOBAL(unordsf2):
+ flds fr5,fpul
+ sts fpul,r4
+ shll r4
+ mov.l LOCAL(c_SF_QNAN_MASK),r1
+ shlr r4
+ cmp/eq r4,r1
+ bt/s LOCAL(unord_next)
+ not r4,r0
+ tst r1,r0
+ bt LOCAL(unord)
+LOCAL(unord_next):
+ flds fr4,fpul
+ sts fpul,r5
+ shll r5
+ shlr r5
+ cmp/eq r5,r1
+ bt/s LOCAL(unord_fail)
+ not r5,r0
+ tst r1,r0
+LOCAL(unord):
+ rts
+ movt r0
+LOCAL(unord_fail):
+ rts
+ mov #0,r0
+ .balign 4
+LOCAL(c_SF_QNAN_MASK):
+ .long 0x7f800000
+ ENDFUNC(GLOBAL(unordsf2))
+#endif /* L_unordsf2 */
+
#endif /* __SH_FPU_ANY__ */
