Hello, I have a question regarding the process of bundling and NOPs insertion for VLIW architecture and I appreciate your answer:
I am calling the second scheduler from the machine reorg pass; similar to what is done for IA64. I now want to handle the bundling and NOPs insertion for VLIW architecture with issue rate of 4 and I want to make sure I understand the process: IIUC I can use the insns with TImode that the scheduler marked to indicate a new cycle, so the the question is how many nops to insert after that cycle, if any. I noticed the following approach that was used in c6x which is mentioned in: http://archiv.tu-chemnitz.de/pub/2004/0176/data/index.html "NOP Insertion and Parallel Scheduling If the scheduler is run, it checks dependencies and tries to schedule the instructions as to minimize the processing cycles. The hooks TARGET_SCHED_REORDER(2) are considered to reorder the instructions in the ready cue in case the back end wants to override the default rules. I used the hooks to memorize the program cycle the instruction is scheduled. This value is stored in a hash table I created for that purpose. From the cycle information I can later determine how many NOPs have to be inserted between two instructions. This value then overrides the attribute value." IA64 seems to have much more complicated approach for the bundling and NOPs insertion and I wonder if the reason is due to IA64 specific issues? or there is something I'm missing in the approach mentioned above? Thanks in advance, Revital
