This question is in response to Ian's answer here:
Ref: http://gcc.gnu.org/ml/gcc/2009-07/msg00462.html
Adding to the referenced inquiry, there are on the machine a condition
codes register for each register.
I would like to model this by writing define_insns in such a way as to
access a register in different modes, i e
r0 | r1 | r2
...................
accumulator0
So that QImode would mean r0, HImode r0+r1, and CCmode would mean r2
(the corresponding cc-reg).
Then, something like this might work:
[(set (match_operand:HI 0 "register_operand" "=a")
(minus:HI (match_operand:HI 1 "register_operand" "a")
(match_operand:HI 2 "register_operand" "a"))
)
(clobber (match_operand:CC 3 "register_operand" "=0")) ]
This way, GCC would always clobber the corresponding cc-register.
Is this possible to implement, in terms of defining a new mode? The
trick would be to add a new register next to the register-pair in the
hard registers definition array, so as to always reference the cc-reg
with an offsetting mode.
I tried this a bit, but reload would refuse it.
I would appreciate comments on this,
/Jonas Paulsson,
LTH, Sweden
(Thesis project)
