On 08/28/2009 06:51 AM, Mohamed Shafi wrote:
Hello all,
I am trying to port a 32bit arch in GCC 4.4.0. My target has support
for 1bit, 2bit shift and add operations. I tried to write patterns for
this , but gcc is not generating those. The following are the patterns
that i have written in md file:
(define_insn "shift_add_<mode>"
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 3 "register_operand" "")
(ashift:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))]
""
"shadd1\\t%1, %0"
)
...
> Is GCC generating patterns with multiply due to
> cost issues? I havent mentioned any cost details.
No, it's merely using multiply because someone way back when
decided that should be the canonical way to represent this.
We canonicalize patterns so that the target file doesn't have
to match both shifts and multiplies.
So your insn should look like:
(define_insn "*shadd1_si"
[(set (match_operand:SI 0 "register_operand" "r")
(plus:SI (mult:SI (match_operand:SI "register_operand" "r")
(const_int 2))
(match_operand:SI "register_operand" "0")))]
""
"shadd1 %1,%0")
This should match even if your target doesn't support a
hardware multiply insn.
See also the shift-add patterns on the Alpha port. There we
have 2 & 3 bit shifts. Search for const48_operand to find
those patterns easily.
r~
