Hi!
I'd appreciate some input on how to get the pipeline scheduler to
know about the bizarre MaverickCrunch timing characteristics.
Brief: Crunch is an asynchronous ARM coprocessor which has internal
operations from/to its own register set, transfers between its own
registers and the ARM integer registers, and transfers directly
to/from memory.
Softfp is the current favourite ABI, where double arguments are
passed in ARM register pairs, same as softfloat, and a typical double
float function transfers its arguments from ARM registers to the FPU,
does some munging between the FPU registers, then transfers the result
back to ARM regs for the return(). It has to do this 32 bits at a
time:
double adddf(double a, double b) {return (a+b);}
adddf:
cfmv64lr mvdx0, r0
cfmv64hr mvdx0, r1
cfmv64lr mvdx1, r2
cfmv64hr mvdx1, r3
cfaddd mvdx1, mvdx1, mvdx0
cfmvr64l r0, mvdx1
cfmvr64h r1, mvdx1
bx lr
Although you can do one transfer per cycle between the two units, two
consecutive transfers to the same Crunch register incur a delay of
four cycles, so each transfers to crunch registers takes 4 cycles. A
better sequence would be:
cfmv64lr mvdx0, r0
cfmv64lr mvdx1, r2
cfmv64hr mvdx0, r1
cfmv64hr mvdx1, r3
My questions are two:
- can I model the fact that two consecutive writes to the same
register have a latency of four cycles (whereas writes to different
registers can be one per cycle)?
- am I right in thinking to define two new register modes, MAVHI and
MAVLO for the two kinds of writes to the maverick registers, then turn
the movdf (and movdi) definitions for moves to/from ARM registers into
define_split's using the two new modes?
Thanks, sorry it's a bit osbcure!
M
"An expert is someone who knows more and more about less and less:
