Hi there. The port that I'm working on has pointer registers backed by a cache. It's unusual as the cache changes immediately when the pointer register is modified instead of later when it is deferenced. This means that it is cheaper to copy a base address into the pointer register, then add the offset as it is less likely that the cache row will change.
Normal code such as this: --- struct abc { int a; char cc[64]; int b; }; int foo(struct abc *p) { return p->a + p->b; } --- generates the correct code: LOADACC, R10 STOREACC, X LOADLONG, #68 ADD, X LOADACC, (X) Code that saves or loads a value into a spill slot however does the opposite: LOADLONG, #16 STOREACC, X LOADACC, R1E (the stack pointer) ADD, X LOADACC, R10 STOREACC, (X) I did a spot check on the bfin port and it does the same: P2 = -16 (X); P2 = P2 + FP; R0 = [P2]; Is there a way of setting the order that reload generates a spill slot address? I can work around it by implementing LEGITIMIZE_RELOAD_ADDRESS but was wondering if there is a better way. Thank you, -- Michael