Thanks, that worked. I ended up using:
(define_insn "cmpcc_xor"
[(set (match_operand:CC 0 "register_operand" "=C")
(compare:CC
(not:SI (xor:SI (match_operand:SI 1 "register_operand" "%r")
(match_operand:SI 2 "register_operand" "b")))
(const_int 0)))
(set (match_operand:SI 3 "register_operand" "=1")
(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
""
"XOR, %1"
)
The important thing was in the generation. The XOR is two operand but
I needed to supply a third pretend operand using:
emit_insn (gen_cmpcc_(cc_reg, x, y, gen_reg_rtx(SImode)));
Using a match_dup instead of operand 3 above, or supplying 'x' twice,
lead to the compiler not noticing the change.
-- Michael
2009/5/18 Jim Wilson <wil...@codesourcery.com>:
> Michael Hope wrote:
>>
>> * Using a define_insn to mark it as both a destructive xor and
>> compare in parallel, such as:
>
> When a compare is in a parallel, the compare must be the first operation.
> You have it second. This kind of pattern should work. You can find many
> examples of it in the sparc.md file for instance. Of course, in this case,
> they aren't generated at RTL generation time. They are generated at combine
> time. Still, I'd expect this to work, though there might be some early RTL
> optimization passes that are not prepared to handle it.
>
> See for instance the cmp_cc_xor_not_set pattern in the sparc.md file, which
> is similar to what you want.
>
> Jim
>
