Kenneth Zadeck <zad...@naturalbridge.com> writes:
> Would those that know, (or even those that are just generally vocal) be
> willing to support a change rtl.texi for sign_extract (and by
> implication, zero_extract) from
>
> If @var{loc} is in memory, its mode must be a single-byte integer mode.
> If @var{loc} is in a register, the mode to use is specified by the
> operand of the @code{insv} or @code{extv} pattern
> (@pxref{Standard Names}) and is usually a full-word integer mode,
> which is the default if none is specified.
>
> to a version that explicitly prohibits the use of a mode longer than a word?
>
> The back ends do not appear to support this anyway.
I guess the obvious counterexample would be a processor which supported
vector registers and supported bitfield operations on such registers. I
don't know of any such processors. The restriction would probably be
fine in practice, but why do you want to make it?
Ian
